Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.5 64-Bit PCI OperationBoth the PATU and the SATU are capable of PCI 64-bit operation to support data transfer rates ofup to 528 MBytes/sec. The 64-bit PCI extensions add 39 additional signals to each ATU PCIinterface. These signals and there functions are• AD[63:32] - high order address/data bus• C/BE[7:4]# - byte enables covering high order 4 bytes of data• PAR64 - even parity signal covering AD[63:32] and C/BE[7:4]#. Same timing as PAR• REQ64# - used by a 64-bit master to request a 64-bit operation. Same timing as FRAME#• ACK64# - used by a 64-bit capable target in response to REQ64# being asserted. Signifies tothe master that the transaction can be completed with 64-bit transfers. Same timing asDEVSEL#.At PCI bus reset, each individual PCI bus (primary and secondary) independently samples theirrespective REQ64# signals. If this signal is low, the bus is 64-bit capable. The PCI to PCI BridgeUnit holds the information about 64-bit bus capability latched at the de-assertion of reset. ThePrimary Bus 64-Bit Capable bit (bit 8) of the Extended Bridge Control Register (EBCR) tells thePATU whether or not the bus it is connected to is 64-bit capable. The Secondary Bus 64-BitCapable bit (Bit 9) of the Extended Bridge Control Register (EBCR) tells the SATU when thesecondary bus is 64-bit capable. Refer to the Chapter 4, “PCI-to-PCI Bridge Unit” for details.5.2.5.1 64-Bit ProtocolThe 64-bit PCI extensions have been developed to coincide with the existing 32-bit protocol. Theadditional 32 bits of address/data require an additional 4 byte enables and a parity signal to coverthem. The bus timing, protocol, and turn-around cycles behave exactly the same for the 64-bitsignals as they do for the standard PCI interface signals with the exception of the 64-bit handshakesignals referenced below.The 64-bit handshake signals used by the Intel ® 80312 I/O companion chip are P_REQ64# andP_ACK64# on the primary interface and S_REQ64# and S_ACK64# on the secondary interface.Asamaster,aPCIinterfaceoftheATUsassertsREQ64# with FRAME# to indicate to the targetthat a 64-bit transaction is being requested. REQ64# is asserted and deasserted with the exacttiming as FRAME# for the master state machines. When REQ64# is asserted, the target of thememory operation is required to assert ACK64# with the same timing as DEVSEL# to allow a64-bit transaction to proceed. If ACK64# is not asserted with DEVSEL#, the master interfacemust revert to a 32-bit transaction. See Section 5.2.5.2 for details on 64-bit operation with 32-bittargets.When ACK64# is asserted by the target of the transaction, a 64-bit transfer must proceed. Asstated, a 64-bit transfer behaves exactly the same as a 32-bit transfer except that up to 8 bytes ofdata are transferred during each PCI data phase. For the 64-bit transfer, the AD[63:32] andC/BE[7:4]# are reserved during the address phase (assuming a SAC transfer). During the dataphases, the master interface transfers up to 8 bytes of data on each of the 8 byte lanes defined byC/BE[7:4]#. As in a 32-bit transfer the master is capable of asserting any (or none) of the byteenables during each of the data phases within a burst transfer. Refer to Figure 5-8 for a diagram ofa 64-bit transfer from a 64-bit target. PAR64 for a 64-bit transfer has the same function and timingas PAR for a 32-bit transfer. PAR64 must be asserted one clock after each address and data phase.64-bit targets qualifies address parity checking using PAR64 with the assertion of REQ64#.Although AD[63:32] and C/BE[7:4]# are reserved for SAC 64-bit transfers, parity must still bepreserved and therefore stable values must be driven.Developer’s Manual 5-25