Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.6 Outbound Doorbell Register - ODRThe Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel ®80200 processor to generate PCI interrupts to the host processor by writing to the SoftwareInterrupt bits or to a specific PCI interrupt bit. The generation of PCI interrupts through theOutbound Doorbell Register may be masked by setting the Outbound Doorbell Interrupt Mask bitin the Outbound Interrupt Mask Register.The Software Interrupt bits in this register can only be set by the Intel ® 80200 processor and canonly be cleared by an external PCI agent.Table 6-12.Outbound Doorbell Register - ODR3128 24 20 16 12 8 4 0PCI IOPAttributes AttributesrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcrsrcODRIntel ® 80200 Processor Local Bus Address132CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionPCI Interrupt D - When set, this bit causes the P_INTD# signal to be asserted. When31 0 2 this bit is cleared, the P_INTD# signal is deasserted.PCI Interrupt C- When set, this bit causes the P_INTC# signal to be asserted. When30 0 2 this bit is cleared, the P_INTC# signal is deasserted.PCI Interrupt B- When set, this bit causes the P_INTB# signal to be asserted. When29 0 2 this bit is cleared, the P_INTB# signal is deasserted.PCI Interrupt A- When set, this bit causes the P_INTA# signal to be asserted. When28 0 2 this bit is cleared, the P_INTA# signal is deasserted.27:00 000000HSoftware Interrupt - When any bit is set, generate a PCI interrupt. The PCI interruptpin used is determined by the ATU Interrupt Pin Register. When all bits are clear, donot generate a PCI interrupt.Developer’s Manual 6-23