Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.4.6 Special CyclesThe bridge unit will neither initiate nor accept PCI Special Cycle commands on either the Primaryor the Secondary interface, except as a conversion. A mechanism is provided for converting Type 1write commands to Special Cycles on either interface. See Section 4.4.4 for details.4.4.7 Extended Configuration SpaceThe bridge unit includes an 8-byte extended configuration space. The extended configuration spacecan be accessed by a device on the Primary interface through a mechanism defined in the PCILocal Bus Specification, Revision 2.2.In the bridge Primary Status Register (Section 4.15.4) the appropriate bit is set indicating that theExtended Capability Configuration space is supported. When this bit is read, the device can thenread the Capabilities Pointer register (Section 4.15.21) to determine the configuration offset of theExtended Capabilities Configuration Space.The first byte at the Extended Configuration Offset is the Capability Identifier Register(Section 4.15.36). This will identify this Extended Configuration Header space as the type definedby the PCI Bus Power Management Interface Specification, Revision 1.1.Following the Capability Identifier Register will be the single byte Next Item Pointer Register(Section 4.15.37) which will indicate the configuration offset of an additional ExtendedCapabilities Header, when supported. In the bridge, the Next Item Pointer Register is set to 00Hindicating that there are no additional Extended Capabilities Headers supported in the bridgeconfiguration space.4.5 Address DecodingThe Intel ® 80312 I/O companion chip provides three separate address ranges that are used todetermine which memory and I/O addresses are forwarded in either direction across the bridgeportion of the Intel ® 80312 I/O companion chip. There are two address ranges provided formemory transactions and one address range provided for I/O transactions. The bridge uses a baseaddress register and limit register to implement an address range. The address ranges are positivelydecoded on the Primary interface with any address within the range considered a Secondaryaddress and therefore capable of being forwarded downstream across the bridge. On the Secondaryinterface, the address ranges are inversely decoded.In addition to the memory and I/O space, the bridge unit implements support for an ISAcompatibility mode to support downstream expansion bridges and support for VGA graphicsdevices on the secondary interface of the bridge.Standard bridge unit address decoding can also be modified by the Secondary Decode EnableRegister (SDER). The bits within this register enable private address space on the Secondary sideof the bridge.The bridge will not accept PCI transactions generated by the Address Translation Units or theDMA Controller from the Secondary PCI interface. The bridge is capable of mastering transactionson the Primary interface that can be accepted by the Primary Address Translation Unit. (seeChapter 5, “PCI Address Translation Unit”.)Developer’s Manual 4-15