Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip5.2.1.4 Inbound Configuration Cycle Translation..................................................5-135.2.1.5 Discard Timers..........................................................................................5-145.2.2 Outbound Transactions ..........................................................................................5-145.2.2.1 Outbound Address Translation .................................................................5-155.2.2.2 Outbound Address Translation Windows..................................................5-155.2.2.3 Direct Addressing Window ........................................................................5-195.2.2.4 Outbound Write Transaction .....................................................................5-205.2.2.5 Outbound Read Transaction.....................................................................5-215.2.3 Private PCI Address Space / Outbound Configuration Cycle Translation ..............5-235.2.4 PCI Multi-Function Device Swapping/Disabling......................................................5-245.2.5 64-Bit PCI Operation...............................................................................................5-255.2.5.1 64-Bit Protocol ..........................................................................................5-255.2.5.2 64-Bit Operation with 32-Bit Targets.........................................................5-275.2.6 66 MHz Operation...................................................................................................5-295.3 Messaging Unit........................................................................................................................5-305.4 Expansion ROM Translation Unit ............................................................................................5-315.5 ATU Queue Architecture .........................................................................................................5-325.5.1 Inbound Queues .....................................................................................................5-325.5.1.1 Inbound Write Queue Structure ................................................................5-335.5.1.2 Inbound Read Queues and Inbound Transaction Queues .......................5-345.5.1.3 Inbound Delayed Write Queue..................................................................5-355.5.2 Outbound Queues ..................................................................................................5-355.5.3 Transaction Ordering..............................................................................................5-365.6 ATU Error Conditions ..............................................................................................................5-395.6.1 Address Parity Errors on the PCI Interface.............................................................5-405.6.2 Data Parity Errors on the PCI Interface ..................................................................5-415.6.2.1 Outbound Read Data Parity Errors - Master.............................................5-415.6.2.2 Outbound Write Data Parity Errors - Master .............................................5-425.6.2.3 Inbound Read Data Parity Errors - Slave..................................................5-425.6.2.4 Inbound Write Data Parity Errors - Slave..................................................5-425.6.2.5 Inbound Configuration Write Data Parity Errors - Slave ...........................5-435.6.3 Master Aborts on the PCI Interface ........................................................................5-445.6.4 Target Aborts on the PCI Interface.........................................................................5-455.6.5 SERR# Assertion and Detection.............................................................................5-465.6.6 Internal Bus Error Conditions..................................................................................5-485.6.6.1 Master Abort on the Internal Bus ..............................................................5-485.6.6.2 Target Abort on the Internal Bus...............................................................5-505.6.7 ATU Error Summary ...............................................................................................5-515.7 Register Definitions .................................................................................................................5-555.7.1 ATU Vendor ID Register - ATUVID.........................................................................5-615.7.2 ATU Device ID Register - ATUDID.........................................................................5-625.7.3 Primary ATU Command Register - PATUCMD ......................................................5-635.7.4 Primary ATU Status Register - PATUSR................................................................5-645.7.5 ATU Revision ID Register - ATURID ......................................................................5-665.7.6 ATU Class Code Register - ATUCCR ....................................................................5-675.7.7 ATU Cacheline Size Register - ATUCLSR .............................................................5-685.7.8 ATU Latency Timer Register - ATULT....................................................................5-695.7.9 ATU Header Type Register - ATUHTR...................................................................5-705.7.10 Primary Inbound ATU Base Address Register - PIABAR .......................................5-715.7.11 ATU Subsystem Vendor ID Register - ASVIR ........................................................5-725.7.12 ATU Subsystem ID Register - ASIR .......................................................................5-73viiiDeveloper’s Manual