Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.13 Secondary Latency Timer Register - SLTRSecondary Latency Timer Register bits adhere to the definitions in the PCI Local BusSpecification, Revision 2.2 and apply to the Secondary interface of the bridge only. It loads a timerat the beginning of each PCI transaction initiated by the bridge on the Secondary bus. When thetimer counts down to zero, the bridge must terminate the transaction as soon as the GNT# signal isdeasserted.Table 4-36.Secondary Latency Timer Register - SLTRIOPAttributes7 4 0rw rw rw rw rw ro ro roPCIAttributesrw rw rw rw rwrororoPCI Configuration Offset1BHIntel ® 80200 Processor Local Bus Address0000 101BHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionProgrammable Latency Timer - This portion of the register varies the latency timer for the Secondary07:03 00000 2 interface from a minimum of zero clocks to a maximum of 248 clocks.Latency Timer Granularity - These bits are read only giving a programmable granularity of eight clocks02:00 000 2 for the Latency Timer.4-98 Developer’s Manual