Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.3 Private PCI Address Space / Outbound Configuration CycleTranslationThe secondary ATU contains special support for private address spaces on the secondary PCI bus.A private address space is defined as a range of secondary PCI bus addresses which are not part ofthe secondary PCI address space as defined by the bridge and are also not part of the primary PCIaddress space. Private address space can be considered a “hole” in the PCI address space that isonly supported on the secondary PCI bus. Private address space generally falls within the primaryPCI address space and requires special bridge support so that it does not forward these addresses.The Intel ® 80312 I/O companion chip has several mechanisms to support private address space:• Inbound transactions from private devices through the secondary ATU.• Outbound transactions from the secondary ATU and DMA channel 2 to private devices.• Outbound configuration cycles to private devices.• Hiding private devices from PCI Type 0 configuration cycles. (See Chapter 4, “PCI-to-PCIBridge Unit” for more details.)For inbound transactions from private devices, the secondary ATU can be configured outside thevalid secondary PCI address space; this creates private address space. The secondary ATU claimsprivate addresses and prevents the bridge from forwarding them upstream to the primary PCI bus.For outbound transactions from the secondary ATU and DMAs, the programmer needs to define aprivate memory address range (see Section 4.5.6, “Private Address Space” on page 4-24) toprevent the bridge from forwarding these transactions upstream to the primary PCI bus.Outbound configuration cycles — secondary and primary — can support private PCI devices.Outbound ATUs provide a port programming model for outbound configuration cycles. Performingan outbound configuration cycle to either the primary or secondary PCI bus involves up to twointernal bus cycles:1) Writing the Outbound Configuration Cycle Address Register (primary or secondary) with thePCI address used during the configuration cycle. See the PCI Local Bus Specification,Revision 2.2 for information regarding configuration address cycle formats. This IB bus cycleenables the transaction.2) Writing or reading the Outbound Configuration Cycle Data Register (primary or secondary).The Intel ® 80200 processor cycle initiates the transaction. A read causes a configuration cycleread to the primary or secondary PCI bus with the address in the outbound configuration cycleaddress register. Similarly, a write initiates a configuration cycle write to PCI with the writedata from the second processor cycle. Configuration cycles are non-burst and restricted to asingle 32-bit word cycle. Internal bus burst writes and reads to the Outbound ConfigurationCycle Data Register are disconnected after the first data phase.Master aborts during outbound configuration reads result in master aborts being returned on theinternal bus.When the Configuration Cycle Data Register is written, the data is latched and forwarded to thePCI bus with the internal master issuing a disconnect with data for 32-bits only. This cycle isdefined as 32-bit only.When the Configuration Cycle Data Register is read, the internal bus master is retried and thedelayed cycle is issued. Refer to Section 5.2.2.5 for details on outbound read behavior.Developer’s Manual 5-23