Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.6.16 Refresh Frequency Register - RFRThe Refresh Frequency Register is programmed for refreshing the SDRAM subsystem at thespecified interval. Writing to the RFR programs the refresh counter with the number of clocksbetween refresh cycles. Reading from the RFR results in the value currently within the refreshcounter.For 100MHz operation, the RFR should be programmed with a value of 600H. For frequenciesbelow 100MHz, the RFR should be programmed with 400H.Table 3-33.Refresh Frequency Register - RFRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw ro ro ro roPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address1568HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:11 0 Reserved10:00 000HRefresh Interval: Programs the number of clocks that triggers a refresh cycle to the SDRAMinterface. When all zeroes, refresh cycles are disabled. See Section 3.2.1.6, “Refresh Counter” onpage 3-4.Developer’s Manual 3-61