Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.7.2 64/32-bit Unaligned Data TransfersFigure 9-8 illustrates a DMA transfer between an unaligned 32-bit source address and an unaligned64-bit destination address.Figure 9-8.Optimization of an Unaligned DMAMSBLSBMSBADDRESS32-bit Source bus(PCI Bus)3726154A000 0200HA000 0204H111510149138 A000 0208H12A000 020CH16 A000 0210H64-bit Destination bus(internal bus)51341231121019 8 7 64001 0300H4001 0308H16 15 144001 0310HProgrammed ValuesCCR 0000 0001HPADR A000 0201HPUADR 0000 0000HLADR 4001 0303HBCR 0000 0010H10byte numberSOURCEword load@ A0000200word load@ A0000204word load@ A0000208word load@ A000020Cword load@ A0000210Bus operationDESTINATION5-byte store@ 400103038-byte store@ 400103083-byte store@ 40010310DCR0000 0006H9.8 Channel PriorityThe Intel ® 80200 processor internal bus arbitration logic determines which internal bus master hasaccess to the internal bus. Each DMA channel has an independent bus Request/Grant signal pair tothe internal bus arbitration. Chapter 7, Intel ® 80312 I/O Companion Chip Arbitration furtherdescribes the priority scheme between all the bus masters on the internal bus. Also described is thepriority mechanism used between the three DMA channels.9-18 Developer’s Manual