Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.1 Accelerator Control Register - ACRThe Accelerator Control Register (ACR) specifies parameters that dictate the overall operatingenvironment. The ACR should be initialized prior to all other AAU registers following a systemreset. Table 10-4 shows the register format. This register can be read or written while the AAU isactive.Table 10-4.Accelerator Control Register - ACRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rwPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address1800HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:03 0 Reserved02 0 2512 Byte Buffer Enable - when set, causes the AAU to use only 512 bytes of the 1KB data buffer whileprocessing all descriptors.NOTES: The 1KB data buffer consumes 128 data cycles on the Internal bus every time the AAU isgranted the Internal Bus (assuming BC remains > 1K). Depending on the application, overallperformance may be improved by throttling down the IB usage to 64 data cycles per Internal Bus grant.01 0 • The AAU completes a transfer and the Accelerator Next Descriptor Address Register is non-zero. InChain Resume - when set, causes the AAU to resume chaining by re-reading the current descriptorlocated at the address in the Accelerator Descriptor Address Register when the AAU is idle (AAU Activebit in the ASR is clear) or when the AAU completes a transfer. This bit is cleared by hardware wheneither:2this case, the AAU proceeds to the next descriptor in the chain.• The AAU re-reads the chain descriptor located at the address in the Accelerator Descriptor AddressRegister and loads the Next Descriptor Address of that descriptor into the Accelerator NextDescriptor Address Register00 0 2AAU Enable - When set, the AAU enables transfers. When clear, the AAU disables any transfer.Clearing this bit when the AAU is active suspends the current transfer at the earliest opportunity byhalting all internal bus transactions. The AAU does not initiate any new transfers when this bit is cleared.Data held in queues remains valid. Setting the bit after the AAU is suspended causes the AAU toresume the previously ongoing transfer.10-24 Developer’s Manual