Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.5 PCI Read TransactionsThe Intel ® 80312 I/O companion chip supports memory read and I/O read transactions from bothsides of the bridge unit. Memory read transactions are claimed when they are within theMBR/MLR or PMBR/PMLR address pairs on the Primary bus and outside the register pairs on theSecondary bus. I/O read transactions are claimed when they are within the IOBR/IOLR writetransactions on the Primary bus and outside the address pair on the Secondary bus. Refer to the PCILocal Bus Specification, Revision 2.2 for full details on memory and I/O read transactions.Prefetchable Memory read commands will be attempted as 64-bit transactions (see Section 4.6.3).I/O, non-prefetchable reads and configuration reads are always performed as 32-bit operations.Refer to Section 4.7.1 for information on bridge queue operation during PCI read operations.The bridge implements Delayed Read transactions in order to meet initial transaction latencyrequirements (from initiating bus IRDY# active to target bus TRDY# active). Delayed Transactionoperation is described in Section 4.6.2.2.The Delayed Read Request (DRR) transaction is the initial memory read or I/O read transactionthat the bridge claims. The address, command, and byte enables of this transaction will be latchedby the bridge and retained in the Transaction Queues. Once the bridge interface latches the address,command (including REQ64# for 64-bit transfers), and byte enables, it will signal a Retry to theinitiator who is then required to re-issue the now delayed request.When the DRR is accepted by the bridge, the bridge will then initiate the transaction on the targetbus. Delayed Requests are accepted as new requests when all of the following conditions apply:• The DRR does not match any DRRs currently held by the bridge in the initiating busTransaction Queues.• The request does not match up with the Delayed Completion currently held by the bridge. Thisnew request must be checked against possible Delayed Completions to see when this is arepeated request that can be completed.• The bridge has the ability to hold a Delayed Read Request in an available Transaction Queueand Delayed Read Completion Queue. In the situation where no queues are available, thebridge will signal a Retry without latching any information.Two requests will match only when they have the exact same address, command, byte enables, andREQ64#. For the purposes of matching a delayed request with a delayed completion, the bridgeunit will not compare byte enables for all prefetchable transactions that have linear addresses. Byteenables will be compared for prefetchable transactions that are non-linear.When the request is accepted as a delayed transaction, the bridge retrys the master on the initiatingbus and performs the same memory or I/O read command on the target bus. When the request is notaccepted, the bridge signals a Retry to the master on the initiating bus with no action on the target bus.When the target returns data on the target bus, the bridge will store the data in a Delayed ReadCompletion (DRC) Queue along with the associated Delayed Request information (address,command, REQ64#, and byte enables) that already exists in the Transaction Queue. The bridgewill accept 1 or more data bytes to be stored in the DRC Queues. When additional queue spacebecomes unavailable (either from physically full or due to reserved space) and more data words areavailable from the target, the bridge will signal a Disconnect on the target bus.The amount of data the bridge reads on the target bus and store in the DRC queues depends on:• PCI command type• whether the memory address space is prefetchable or not• Size of Delayed Read Completion Queues available for dataDeveloper’s Manual 4-37