Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.5.12 M4_SPCI_IOP_gntThis occurrence event monitors the number of times the Intel ® 80312 I/O companion chip isgranted the secondary PCI bus. It increments the counter when the Intel ® 80312 I/O companionchip is the secondary PCI bus master. The counter is incremented once for every new transaction.For multi-cycle transactions, the counter increments once on the first cycle. The count value is asummation of the individual grants received by the bridge, satu and dma Ch-2.11.3.5.13 M4_SPCI_IOP_acqThis duration event counts number of clocks spent by the Intel ® 80312 I/O companion chip(includes the bridge, dma Ch-2, and satu) acquiring the secondary PCI interface. The counterincrements on every clock cycle after the Intel ® 80312 I/O companion chip has requested use ofthe secondary PCI bus but has not actively driven the secondary PCI bus as a master. The counteralso increments for all clock cycles when this agent’s Request Signal is asserted but bus ownershipcurrently belongs to another master. This is an event primitive, used in conjunction with anotherevent primitive (number of grants granted to the Intel ® 80312 I/O companion chip) to calculate theaverage acquisition latency for the processor.11.3.5.14 M4_SPCI_IOP_ownThis duration event counts the duration for which the Intel ® 80312 I/O companion chip is themaster on the secondary PCI interface. The counter increments on every clock cycle during whichthe Intel ® 80312 I/O companion chip is the bus master.11.3.6 Mode 5: Intel ® 80312 I/O Companion Chip Bus and AgentsEventsProgramming Mode 5 (M5) in ESR, enables Intel ® 80312 I/O companion chip performance monitoringon internal bus. In addition, performance monitoring is done for selected agents. In this mode,monitored agents are: DMA channels (Ch-0, Ch-1 and Ch-2) and Application Accelerator. All countersare clocked at internal bus frequency. The following sections describe monitored events in Mode 5.11.3.6.1 M5_IBus_idleThis duration event increments the counter every internal bus idle cycle. An idle cycle occurs whenthere is no activity on the bus due to data being transferred and/or the bus is not in an overheadcycle. An overhead cycle is a cycle when a master owns the bus, however the master is unable tosend data or the target is unable to receive data - hence no data is transferred.11.3.6.2 M5_IBus_busyThis duration event increments the counter on every internal bus data cycle. This enablescalculation of data utilization of the bus.Developer’s Manual 11-15