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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Introduction1.3 FeaturesThe <strong>Intel</strong> ® <strong>80312</strong> I/O companion chip together with the <strong>Intel</strong> ® 80200 processor provides a costeffective solution that addresses the needs for intelligent I/O designs. This multi-function PCIdevice is fully compliant with the PCI Local Bus Specification,Revision2.2.The<strong>Intel</strong> ® <strong>80312</strong> I/Ocompanion chip specific features include:• PCI-to-PCI Bridge Unit • I 2 C Bus Interface Unit• Private PCI Device Support • Performance Monitoring Unit• DMA Controller • Secondary PCI Arbitration Unit• Address Translation Unit • Messaging Unit• Memory Controller • I 2 O Compatibility• Application Accelerator UnitThe subsections that follow briefly overview each feature. Refer to the appropriate chapter for fulltechnical descriptions.1.3.1 PCI-to-PCI Bridge UnitThe PCI-to-PCI bridge unit (referred to as “bridge”) connects two independent PCI buses. It isfully compliant with the PCI-to-PCI Bridge Architecture Specification, Revision 1.1 published bythe PCI Special Interest Group. It allows certain bus transactions on one PCI bus to be forwarded tothe other PCI bus. It allows fully independent PCI bus operation and fully supports 32-bit or 64-bitbus widths. Dedicated data queues support high performance bandwidth on the PCI buses. Theprimary and secondary PCI buses may independently be configured as 32-bit or 64-bit wide. The<strong>Intel</strong> ® <strong>80312</strong> I/O companion chip supports PCI 64-bit Dual Address Cycle (DAC) addressing forupstream transactions.The bridge has dedicated PCI configuration space that is accessible through the primary PCI bus.The bridge also supports the power management extended capability configuration header asdefinedbythePCI Bus Power Management Interface Specification, Revision 1.1 Compliance tothis specification provides the hardware support required by the software initiative defined by theAdvanced Configuration and Power Interface Specification, Revision 1.0 (ACPI).1.3.2 Internal BusThe Internal Bus is a high-speed interconnect between all internal units and controllers. TheInternal Bus operates at 100 MHz and is 64-bits wide.1.3.3 Private PCI Device SupportAkey<strong>Intel</strong> ® <strong>80312</strong> I/O companion chip feature is that it explicitly supports private PCI devices onthe secondary PCI bus without being detected by PCI configuration software. The bridge andAddress Translation Unit work together to hide private devices from PCI configuration cycles andallow these devices to use a private PCI address space. The Address Translation Unit uses normalPCI configuration cycles to configure these devices.1-4 Developer’s Manual

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