Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitFigure 5-3 shows an example of inbound address detection.Figure 5-3.Inbound Address DetectionAddress is not claimedBase_RegisterAddressisclaimedPCI AddressSpaceInbound TranslationWindowse_Register + Value of Limit_RegisterAddress is not claimedThe incoming 32-bit PCI address is bitwise ANDed with the associated inbound limit register.When the result matches the base register, the inbound PCI address is detected as being within theinbound translation window and is claimed by the ATU.Note:The first 4 Kbytes of the primary ATUs inbound address translation window are reserved for theMessaging Unit. PCI addresses in this 4 Kbyte area are not translated and forwarded to the localbus as inbound transactions. See Section 5.3, “Messaging Unit” on page 5-30.Once the transaction is claimed, the address must be translated from a 32-bit PCI address to a32-bit local bus address. The algorithm is:Equation 5-2. Inbound TranslationIntel ® 80312 I/O Companion Chip Internal Bus Address = (PCI_Address & ~Limit_Register) |ATU_Translate_Value_Register.The incoming 32-bit PCI address is first bitwise ANDed with the bitwise inverse of the limitregister. This result is bitwise ORed with the ATU Translate Value and the result is the internal busaddress. This translation mechanism is used for all inbound memory read and write commandsexcluding inbound configuration read and writes. Inbound configuration cycle translation isdescribed in Section 5.2.1.4, “Inbound Configuration Cycle Translation” on page 5-13. Addressaliasing of multiple PCI addresses to the same physical Intel ® 80312 I/O Companion Chip InternalBus address can be prevented by programming the inbound translate value register on boundariesmatching the associated limit register, but this is only enforced through application programming.For inbound memory transactions, the only burst order supported is Linear Incrementing. For anyother burst order, the ATU signals a Disconnect after the first data phase.Developer’s Manual 5-7