Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip3.2 Theory of Operation...................................................................................................................3-33.2.1 Functional Blocks......................................................................................................3-33.2.1.1 Internal Bus Interface..................................................................................3-43.2.1.2 Address Decode .........................................................................................3-43.2.1.3 Configuration Registers ..............................................................................3-43.2.1.4 SDRAM State Machine ...............................................................................3-43.2.1.5 Flash State Machine ...................................................................................3-43.2.1.6 Refresh Counter..........................................................................................3-43.2.1.7 Pipeline Queues and Error Correction Logic ..............................................3-53.2.2 Flash Memory Support .............................................................................................3-53.2.2.1 Flash Memory Addressing ..........................................................................3-73.2.2.2 Flash Read Cycle........................................................................................3-83.2.2.3 Flash Write Cycle......................................................................................3-103.2.3 SDRAM Memory Support .......................................................................................3-113.2.3.1 SDRAM Sizes and Configurations ............................................................3-133.2.3.2 SDRAM Addressing ..................................................................................3-153.2.3.3 Page Hit/Miss Determination ....................................................................3-163.2.3.4 SDRAM Commands..................................................................................3-183.2.3.5 SDRAM Initialization .................................................................................3-193.2.3.6 SDRAM Mode Programming ....................................................................3-203.2.3.7 SDRAM Read Cycle .................................................................................3-213.2.3.8 SDRAM Write Cycle..................................................................................3-243.2.3.9 SDRAM Refresh Cycle .............................................................................3-263.2.4 Error Correction and Detection ...............................................................................3-273.2.4.1 ECC Generation........................................................................................3-273.2.4.2 ECC Generation for Partial Writes ............................................................3-283.2.4.3 ECC Checking ..........................................................................................3-293.2.4.4 Scrubbing..................................................................................................3-313.2.4.5 ECC Testing..............................................................................................3-333.2.5 Overlapping Memory Regions ................................................................................3-333.2.6 SDRAM Clocking....................................................................................................3-343.3 Power Failure Mode ................................................................................................................3-353.3.1 Theory of Operation................................................................................................3-353.3.2 Power Failure Sequence ........................................................................................3-363.3.2.1 Power Failure Impact on the System ........................................................3-363.3.2.2 System Assumptions ................................................................................3-363.3.3 Memory Controller Response to I_RST#................................................................3-373.3.3.1 External Logic Required for Power Failure ...............................................3-393.4 Interrupts/Error Conditions ......................................................................................................3-413.4.1 Single-Bit Error Detection .......................................................................................3-423.4.2 Double-Bit/Nibble Error Detection...........................................................................3-433.5 Reset Conditions .....................................................................................................................3-433.6 Register Definitions .................................................................................................................3-443.6.1 SDRAM Initialization Register - SDIR.....................................................................3-453.6.2 SDRAM Control Register - SDCR ..........................................................................3-463.6.3 SDRAM Base Register - SDBR..............................................................................3-483.6.4 SDRAM Boundary Register 0 - SBR0 ....................................................................3-493.6.5 SDRAM Boundary Registers 1 - SBR1...................................................................3-503.6.6 ECC Control Register - ECCR................................................................................3-513.6.7 ECC Log Registers - ELOG0, ELOG1....................................................................3-523.6.8 ECC Address Registers - ECAR0, ECAR1.............................................................3-533.6.9 ECC Test Register - ECTST...................................................................................3-54ivDeveloper’s Manual