Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.29 Secondary I/O Base Register - SIOBRSecondary I/O Base Register bits are used when the Secondary PCI interface is enabled for privateaddressing. The Secondary I/O Base Register defines the bottom address (inclusive) of a positivelydecoded address range that is used to determine when to not forward I/O transactions from theSecondary interface to the Primary interface of the bridge. It must be programmed with a validvalue before the Private Address Space Enable bit is set. The bridge only supports 16-bitaddressing which is indicated by a value of 0H in the four least significant bits of the register. Theupper 4 bits are programmed with S_AD[15:12] for the bottom of the address range. S_AD[11:0]of the base address is always 000H forcing the Secondary I/O address range to be 4 Kbyte aligned.For the purposes of address decoding, the bridge assumes that S_AD[31:16], the upper 16 addressbits of the I/O address, are zero. The bridge must still perform the address decode on the full 32 bitsof address per PCI Local Bus Specification and check that the upper 16 bits are equal to 0000H.Table 4-50.Secondary I/O Base Register - SIOBRIOPAttributes7 4 0rw rw rw rw ro ro ro roPCIAttributesrw rw rw rwrorororoPCI Configuration Offset54HIntel ® 80200 Processor Local Bus Address0000 1054HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:04 0HSecondary I/O Base Address - This field is programmed with S_AD[15:12] of the bottom of the privateSecondary I/O address range not passed from the Secondary to the Primary side of the bridge due to aprivate I/O range.03:00 0H I/O Addressing Capability - The value of 0H signifies that the bridge only supports 16-bit I/O addressing.4-116 Developer’s Manual