Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.7.1.4 Upstream/Downstream Transaction QueuesThe upstream and downstream Transaction Queues are used to hold the address and commandinformation from a delayed read or delayed write request cycle. The address within the TransactionQueue is latched on the initiating bus and is presented on the target bus during the delayedcompletion cycle. Once the delayed completion cycle is enqueued in the completion queue (datafor reads, status for writes), the Transaction Queue is used in determining which PCI transaction onthe initiating bus is the retried transaction of the original request cycle.The choice of which Transaction Queue for reads (U_TRQ0 - U_TRQ2 and D_TRQ0 - D_TRQ2)is determined from the information in Section 4.7.1.2. The Transaction Queues for write (U_TRQ3and D_TRQ3) are dedicated.The Transaction Queues are loaded during the request cycle on the initiating bus and are onlyinvalidated when a PCI master retries the original request transaction on the initiating interface orwhen a discard timer attached to the associated data queue expires.For Dual Address Cycles initiated on the Secondary interface, the Transaction Queues are capableof holding the upper 32-bits of address in a separate set of queues.4.7.2 Transaction OrderingBecause the bridge can process multiple transactions simultaneously, it must maintain properordering to avoid deadlock conditions and improve throughput. The PCI-to-PCI Bridge transactionordering rules used by the Intel ® 80312 I/O companion chip are listed in Table 4-17.Table 4-17.Bridge Transaction Ordering RulesRow PassColumn?Posted MemoryWrite (PMW)Delayed ReadRequest (DRR)Delayed WriteRequest (DWR)Delayed ReadCompletion(DRC)Delayed WriteCompletion(DWC)Posted MemoryWrite (PMW)Delayed ReadRequest (DRR)Delayed WriteRequest (DWR)Delayed ReadCompletion(DRC)Delayed WriteCompletion(DWC)No Yes Yes Yes YesNo Yes Yes Yes YesNo Yes No Yes YesNo Yes Yes Yes YesYes Yes Yes Yes NoThese transaction ordering rules define base line operation for the way data moves in bothdirections through the PCI-to-PCI Bridge. In Table 4-17 a NO response in a box means, based onordering rules, the current transaction (the row) can not pass the previous transaction (the column)under any circumstance. A Yes response in the box means the current transaction is allowed to passthe previous transaction, but is not required to do so. This table is derived from Appendix E of thePCI Local Bus Specification, Revision2.2.Therulesforwhen a current transaction will pass aprevious transaction (based on a YES in Table 4-17) are defined in Section 4.7.2.In the case of bridge posted memory write operations, multiple transactions may exist within thePMW Queue at any point in time. The ordering of these transactions is based on a time stamp basis.Transactions entering the queue are stamped with a relative time in relation to all other transactionsmoving in a similar direction.4-52 Developer’s Manual