Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipTest FeaturesFigure 14-5.Timing Diagram Illustrating the Loading of Data RegisterTCKTMSControllerStateRun - Test / IdleSelect - DR - ScanCapture - IRShift - DRExit1- DRPause - DRExit2- DRShift - DRExit1- DRUpdate- DRRun - Rest - IdleSelect - DR - ScanSelect - IR - ScanTest-Logic-ResetTDIData Inputto IRIRShift-registerParalleloutput of IRData Inputto TDRInstructionIDCodeTDRShift-registerParalleloutput of TDROld DataNew DataRegisterselectedTest Data RegisterTDOenableInactive Active Inactive ActiveInactiveTDO= Don't Care or UndefinedA6809-0114-26 Developer’s Manual
Request Bus64-Bit I/FI 2 C BusClocking, Reset, and Initialization 15This chapter describes the clocking and reset function. The intent of this chapter is to elaborate andclarify descriptions of the clocking and reset mechanisms.15.1 Clocking OverviewThe Intel ® 80312 I/O companion chip contains various clocking boundaries internally. The clocksfor all of the units within the Intel ® 80312 I/O companion chip are generated from a single inputclock. Clock regions are buffered or PLL versions of this clock input for the processor design. Thisinput feeds the Phase Lock Loop (PLL) circuitry which generates the internal clocks for clockregions 2 and 3.The block diagram of the Intel ® 80312 I/O companion chip shown in Figure 15-1, highlights thefour clocking regions for this processor.Figure 15-1.Intel ® 80312 I/O Companion Chip Clocking Regions DiagramDCLKINDCLKOUTDCLK[3:0]SCLClock Region 3Clock Region 2Core Interface UnitMemoryControllerI 2 CUnitApplicationAccelerator800 MBs Internal Bus (100MHz/64-bit)2 ChannelDMAControllerPrimaryAddressTranslationUnitI 2 0*MessagingUnitPerformanceMonitoringUnit1 ChannelDMAControllerSecondaryAddressTranslationUnitS_CLKOUT[5:0]R_CLKOUTP_CLKR_CLKINClock Region 1Primary PCI BusPCI - to - PCIBridgeSecondary PCI BusSecondaryPCI ArbiterClock Region 46 Reg/Gnt PairsA8289-01Within each of the clocking regions identified exist various clock requirements for the Intel ®80312 I/O companion chip units and for the output clocks pins provided for the external subsystem.Developer’s Manual 15-1
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Application Accelerator Unit 10This
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Intel 80312 I/O Companion Chip - ECEE

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