Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11.4 Discard TimersThe discard timers are responsible for preventing deadlocks when the initiator of a retriedtransaction fails to complete the transaction within 2 10 or 2 15 PCI clock cycles on the initiating bus.The timers start counting when the delayed request becomes a delayed completion by completingon the destination bus. When the originating master on the initiating bus has not retried thetransaction before the associated timer expires, the completion transaction is discarded andP_SERR# is optionally asserted on the Primary bus.There are eight discard timers in the bridge unit. Each PCI interface of the bridge unit has separatediscard timers for a the DRC and DWC Queues in each direction. When the discard timer attachedto a particular queue expires, the queue is invalidated, freeing the queue for use with a newtransaction.The discard timers are controlled through configuration bits in the Bridge Control Register.Delayed cycles initiated from the Primary bus interface have a programmable discard value of 2 10(enabled by setting bit 8 in the BCR) or 2 15 (enabled by clearing bit 8 in the BCR). Delayed cyclesinitiated from the Secondary bus interface have a programmable discard value of 2 10 (enabled bysettingbit9intheBCR)or2 15 (enabled by clearing bit 9 in the BCR).When a discard timer expires, the bridge sets (unconditionally) the Discard Timer Status bit in theBCR and optionally asserts P_SERR# when the following is true:• The SERR# Enable bit is set in the PCR• The Discard Timer SERR# Enable bit is set in the BCRThe Primary and Secondary Discard Timers can be disabled by setting Discard Timer Disable bit(bit 07) in the Extended Bridge Control Register (EBCR). When disabled, the timers will not countand delayed completion transactions will remain in their respective queues until retrieved by a PCImaster.Developer’s Manual 4-73