Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.8.1 M7_IBus_idleThis duration event increments the counter every internal bus idle cycle. An idle cycle occurs whenthere is no activity on the bus due to data being transferred and/or the bus is not in an overheadcycle. An overhead cycle is a cycle when a master owns the bus, however the master is unable tosend data or the target is unable to receive data - hence no data is transferred.11.3.8.2 M7_IBus_busyThis duration event increments the counter every internal bus data cycle. This enables calculationof data utilization of the bus.11.3.8.3 M7_SPCIbus_idleThis duration event increments the counter every secondary PCI bus idle cycle. An idle cycleoccurs when there is no activity on the bus due to data being transferred and/or the bus is not in anoverhead cycle. An overhead cycle is a cycle when a master owns the bus, however the master isunable to send data or the target is unable to receive data - hence no data is transferred.11.3.8.4 M7_SPCIbus_busyThis duration event increments the counter every secondary PCI data cycle. Data cycles compriseof two instances:• The Intel ® 80312 I/O companion chip as a master on the bus is involved in data transfers toother masters.• External masters initiate data transfers to either the Intel ® 80312 I/O companion chip or toother masters on the bus.11.3.8.5 M7_SPCI_IOP_ownThis duration event counts the duration for which the Intel ® 80312 I/O companion chip is themaster on the secondary PCI bus. The counter increments on every clock cycle during which theIntel ® 80312 I/O companion chip is the bus master.11.3.8.6 M7_D0_ownThis duration event counts the duration for which PCI Master 0 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 0 is the bus master.11.3.8.7 M7_D1_ownThis duration event counts the duration for which PCI Master 1 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 1 is the bus master.11.3.8.8 M7_D2_ownThis duration event counts the duration for which PCI Master 2 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 2 is the bus master.11-20 Developer’s Manual