Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.3.2 Initiating DMA TransfersA DMA transfer is started by building one or more chain descriptors in the Intel ® 80200 processorlocal memory. Each chain descriptor takes the form shown in Figure 9-3. The chain descriptors arerequired to be aligned on an 8-word boundary in the Intel ® 80200 processor local memory.The following describes the steps for initiating a new DMA transfer:1. The channel must be inactive prior to starting a DMA transfer. This can be checked bysoftware by reading the Channel Active bit in the Channel Status Register (CSR). When thisbit is clear, the channel is inactive. When this bit is set, the channel is currently active with aDMA transfer.2. The CSR must be cleared of all error conditions.3. The software writes the address of the first chain descriptor to the Next Descriptor AddressRegister.4. The software sets the Channel Enable bit in the Channel Control Register (CCR). Since this isthe start of a new DMA transfer and not the resumption of a previous transfer, the ChainResume bit in the CCR should be clear.5. The channel starts the DMA transfer by reading the chain descriptor at the address containedin the Next Descriptor Address Register. The channel loads the chain descriptor values into thechannel control registers and begins data transfer. The Descriptor Address Register nowcontains the address of the chain descriptor just read and the Next Descriptor Address Registernow contains the Next Descriptor Address from the chain descriptor just read.The last descriptor in the DMA chain list has zero in the next descriptor address field specifying thelast chain descriptor. The NULL value notifies the DMA channel not to read additional chaindescriptors from memory.Once a DMA transfer is active, it may be temporarily suspended by clearing the Channel Enablebit in the CCR. Note that this does not abort the DMA transfer. The channel resumes the DMAtransfer when the Channel Enable bit is set.When descriptors are read from external memory, bus latency and memory speed affect chaininglatency. Chaining latency is defined as the time required for the channel to access the next chaindescriptor plus the time required to set up for the next DMA transfer.See Section 9.9 for a state diagram of the channel programming model.9-8 Developer’s Manual