Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTerm definitions used in Table 5-7 and Table 5-8 (PCI terms noted in parenthesis) are as follows:• Inbound Write (PMW) - Data from a write cycle initiated on PCI and targeted at the internalbus. Note that the address is in a separate transaction queue and is not referenced. Inboundwrites can also come in through the Messaging Unit which is part of the primary ATU.• Inbound Read Request (DRR) - Address information from read transactions retried anddelayed on PCI bus. Mastered on internal bus to retrieve data for Inbound Read Completion.• Inbound Configuration Write Request - (DWR) - Address and data associated with aconfiguration write transaction from primary PCI and targeted at ATU PCI configurationaddress space. Once completed on internal bus, creates an Inbound Configuration WriteCompletion. Only available in the PATU.• Outbound Read Completion (DRC) - Data read on PCI in process of being returned to the CIUon the internal bus. This data is completion cycle resulting from Outbound Read Request.• Outbound Write (PMW) - Address and data from a write initiated on the internal bus andeventually completing on the PCI bus.• Outbound Read Request (DRR) - Address/command of a delayed read cycle initiated on theinternal bus. The read data is returned in the Outbound Read Completion cycle.• Inbound Read Completion (DRC) - Data read on the internal bus in the process of beingreturned to the PCI bus. This data is the completion cycle for an Inbound Read Request.• Inbound Configuration Write Completion (DWC) - Status of an inbound write configurationcycle traveling from internal bus back towards primary PCI bus. Only present in the PATU.These transaction ordering rules define the way data moves in both directions through the ATUs. InTable 5-7 and Table 5-8 a NO response in a box means that based on ordering rules, the currenttransaction (row) can not pass previous transaction (column) under any circumstance. A Yesresponse in box means the current transaction is allowed to pass the previous transaction, but is notrequired to, based on whether a consistent view of data or prevention of deadlocks is needed.In the case of inbound write operations, multiple transactions may exist within the x_IWQ and thecorresponding x_IWQAD at any point in time. The ordering of these transactions is based on atime stamp basis. Transactions entering the queue are stamped with a relative time in relation to allother transactions moving in a similar direction.Example 5-1. Inbound Queue CompletionOutbound Read QueueB B B B B B B BInbound Write QueueC C C C C C C C A A A A A A APCI BusInternal BusOutbound Read QueueB B B B B B B BInbound Write QueueC C C C C C C CA6499-01Developer’s Manual 5-37