Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.6 Glitch Suppression LogicThe I 2 C Bus Interface Unit has built-in glitch suppression logic. Glitches is suppressed accordingto: 6 times the internal bus clock period for a 100 MHz internal bus and 4 times the internal busclock period of slower internal bus frequencies. For example, with a 100 MHz (10 ns period)Intel ® 80312 I/O companion chip clock, glitches of 60 ns or less is suppressed. At 40 MHz (25 nsperiod) clock, glitches of 100 ns or less is suppressed. This is within the 50 ns glitch suppressionspecification.12.7 Reset ConditionsThe I 2 C unit is reset with I_RST#. Software is responsible for ensuring the I 2 C unit is not busy(ISR[3]) before asserting reset. Software is also responsible for ensuring the I 2 C bus is idle whenthe unit is enabled after reset. When directed to reset, the I 2 C unit returns to its default resetcondition with the exception of the ISAR. ISAR is not affected by a reset.When the Unit Reset bit in the ICR is set, only the Intel ® 80312 I/O companion chip I 2 C unitresets, the associated I 2 C MMRs remain intact. When resetting the I 2 C unit with the ICR’s unitreset, use the following guidelines:1. In the ICR register, set the reset bit and clear the remainder of the register.2. Clear the ISR register.3. Clear reset in the ICR.12.8 Register DefinitionsThe following registers are associated with the I 2 C Bus Interface Unit. They are all located withinthe peripheral memory- mapped address space of the Intel ® 80312 I/O companion chip. SeeSection 12.8, “Register Definitions” on page 12-26 for the register addressesTable 12-8.I 2 C Register Summary TableSection, Register Name, PageSection 12.8.1, “I 2 C Control Register- ICR” on page 12-27Section 12.8.2, “I 2 C Status Register- ISR” on page 12-30Section 12.8.3, “I 2 C Slave Address Register- ISAR” on page 12-32Section 12.8.4, “I 2 C Data Buffer Register- IDBR” on page 12-33Section 12.8.5, “I 2 C Clock Count Register- ICCR” on page 12-34Section 12.8.6, “I 2 C Bus Monitor Register- IBMR” on page 12-3512-26 Developer’s Manual