Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipIntroduction1.3.10 I 2 CBusInterfaceUnitThe I 2 C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel ® 80200 processor to serve asa master and slave device residing on the I 2 C bus. The I 2 C unit uses a serial bus developed byPhilips Semiconductor consisting of a two-pin interface. The bus allows the Intel ® 80200 processorto interface to other I 2 C peripherals and microcontrollers for system management functions. Itrequires a minimum of hardware for an economical system to relay status and reliabilityinformation on the I/O subsystem to an external device. Also refer to I 2 C Peripherals forMicrocontrollers (Philips Semiconductor).1.3.11 Secondary PCI Arbitration UnitThe Secondary PCI Arbitration Unit is the arbiter for the secondary PCI bus. It includes a fairnessalgorithm with programmable priorities and six PCI request and grant signal pairs. This arbitrationunit can also be disabled to allow for external arbitration.1-6 Developer’s Manual
Intel ® 80312 I/O Companion ChipIntroduction1.4 Terminology and Conventions1.4.1 Representing Numbers1.4.2 FieldsAll numbers in this document can be assumed to be base 10 unless designated otherwise. In text,numbers in base 16 are represented as “nnnH”, where the “H” signifies hexadecimal. In pseudocode descriptions, hexadecimal numbers are represented in the form 0x1234ABCD. Binarynumbers are not explicitly identified but are assumed when bit operations or bit ranges are used.A reserved field is a field that may be used by an implementation. When the initial value of areserved field is supplied by software, this value must be zero. Software should not modifyreserved fields or depend on any values in reserved fields.A read/write field can written to a new value following initialization. This field can always be readto return the current value.A read only field can be read to return the current value. Writes to read only fields are treated asno-op operations and does not change the current value nor result in an error condition.A read/clear field can also be read to return the current value. A write to a read/clear field with thedata value of 0 causes no change to the field. A write to a read/clear fieldwithadatavalueof1causes the field to be cleared (reset to the value of 0). For example, when a read/clear field has avalue of F0H, and a data value of 55H is written, the resultant field is A0H.A read/set field can also be read to return the current value. A write to a read/set field with the datavalue of 0 causes no change to the field. A write to a read/set field with a data value of 1 causes thefield to be set (set to the value of 1). For example, when a read/set field has a value of F0H, and adata value of 55H is written, the resultant field is F5H.A writeonce/readonly fieldcanbewrittentoanewvalueonce following initialization. After thethis write has occurred, the writeonce/readonly field treats all subsequent writes as no-opoperations and does not change the current value or result in an error condition. The field canalways be read to return the current value.1.4.3 Specifying Bit and Signal ValuesThe terms set and clear in this specification refer to bit values in register and data structures. Whena bit is set, its value is 1; when the bit is clear, its value is 0. Likewise, setting a bit means giving ita value of 1 and clearing a bit means giving it a value of 0.The terms assert and deassert refer to the logically active or inactive value of a signal or bit,respectively.1.4.4 Signal Name ConventionsAll signal names use the PCI signal name convention of using the “#” symbol at the end of a signalname to indicate that the signal’s active state occurs when it is at a low voltage. The absence of the“#” symbol indicates that the signal’s active state occurs when it is at a high voltage.Developer’s Manual 1-7
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Intel ® 80200 Processor based on I
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Intel 80312 I/O Companion Chip - ECEE

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