Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTable 5-1.ATU Command SupportPCI Command TypeClaimed on InboundTransactions on PCIBusGenerated byOutbound Transactionson PCI BusValid Internal BusCommandInterrupt Acknowledge No No NoSpecial Cycle No No NoI/O Read No Yes NoI/O Write No Yes NoMemory Read Yes Yes YesMemory Write Yes Yes YesMemory Write andInvalidateYes No NoMemory Read Line Yes No YesMemory Read Multiple Yes No YesConfiguration Read Yes Yes YesConfiguration Write Yes Yes YesDual Address Cycle No Yes NoInbound and outbound ATU transactions are best described by the data flows used on the PCI busand the Intel ® 80312 I/O companion chip internal bus during read and write operations. Thefollowing sections describe read and write operations for inbound ATU transactions (PCI tointernal bus) and outbound transactions (internal bus to PCI). For the purposes of data flows, thereare no distinctions between primary ATU transactions and secondary ATU transactions.5.2.1 Inbound TransactionsInbound transactions which target the PATU or the SATU are translated and performed on theIntel ® 80312 I/O companion chip internal bus. As a PCI target, the ATUs are capable of acceptingall PCI memory read and write operations as either a 32-bit or a 64-bit target PCI target. Refer toSection 5.2.5 for details on 64-bit PCI operation. Memory Writes and Memory Write and Invalidateoperations are performed as posted operations and all memory read operations are performed asdelayed reads. The PATU is capable of accepting configuration read and write cycles. ForConfiguration Writes, the cycles are performed as delayed memory write operations. ConfigurationReads are performed as delayed read operations.Inbound write transactions have their address entered into the inbound write address queue(IWQAD) and data entered into the inbound write data queue (IWQ). The IWQ/IWQAD pair arecapable of holding up to 4 write operations up to the size of the data queue. Inbound readoperations (memory and configuration) have their address entered into the inbound transactionqueue (ITQ) and the data is returned to the PCI master in the inbound read queue (IRQ). Inboundconfiguration writes use the inbound delayed write queue (IDWQ) for address and data. Refer toSection 5.5 for details of queue operation.For inbound transactions, the ATUs are slaves on the PCI bus and are masters on the internal bus.PCI slave operation is defined in the PCI Local Bus Specification, Revision 2.2.Developer’s Manual 5-5