Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.1 Inbound Message Register - IMRxThere are two Inbound Message Registers: IMR0 and IMR1. When the IMR register is written, aninterrupt to the Intel ® 80200 processor may be generated. The interrupt is recorded in the InboundInterrupt Status Register and may be masked by the Inbound Message Interrupt Mask bit in theInbound Interrupt Mask Register.Table 6-7.Inbound Message Register - IMRxPCI IOPAttributes Attributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rwrw rw rw rw rw rwrw rw rw rw rw rw rw rw rwrw rw rw rw rw rw rw rw rwrw rwrw rwrw rw rw rw rw rw rwrw rw rw rw rw rw rwrwrwrw rw rw rw rw rw rwrw rw rw rw rw rw rwIMR0IMR1Intel ® 80200 Processor Local Bus Address1310H1314HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:00 00000000HInbound Message - This is a 32-bit message written by an external PCI agent. Whenwritten, an interrupt to the Intel ® 80200 processor may be generated.6-18 Developer’s Manual