Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.4 Internal Bus CommandsTable 8-3 contains a summary of the Intel ® 80312 I/O companion chip internal bus commandsused by the CIU.Table 8-3.Intel ® 80312 I/O Companion Chip Internal Bus Command SummaryIB Bus CommandMemory ReadMemory Read LineMemory Read MultipleMemory WriteUsageRead 1, 2, or 4 bytesRead 8 bytesRead 32 bytesFor all writesNote:The CIU detects memory reads from the Intel ® 80200 processor and determines the amount of datarequested by the Intel ® 80200 processor. The CIU then converts the memory read command intodifferent internal bus commands to denote the amount of data requested as described in Table 8-3.8.4.1 ATU AccessesAll read accesses from the CIU to the ATU are processed as Delayed Transactions.There are two sideband Backoff signals between each ATU and the CIU to eliminate wastedinternal bus bandwidth when the CIU receives a Retry from the ATU during a read access. Whenasserted, these Backoff signals indicate that the CIU should “backoff” and wait until the backoffsignal is deasserted before attempting to retry the read access.When the CIU receives a Retry from the Primary ATU, the ATU asserts the Backoff signal. Thissignal indicates that the Primary ATU cannot complete this internal bus access. When the ATU isready to complete the bus access, it deasserts the Backoff signal. The deassertion of the Backoffsignal indicates that the CIU should request the Internal Bus and retry the read access. TheSecondary ATU implements the same logic, but uses a different Backoff signal.Atomic accesses from the CIU to the ATUs are not supported.8.4.2 Atomic AccessesThe CIU supports atomic bus accesses (Locked transactions) from the Intel ® 80200 processor tolocal memory and the Peripheral Memory-Mapped Registers (PMMR). The Intel ® 80200processor asserts the LOCK# signal when performing an atomic transfers (atomic read).During an atomic access from the Intel ® 80200 processor to local memory or PMMR, the CIUasserts a signal to the Internal Bus Arbiter, indicating an atomic access is in progress. The signalstays asserted until all bus accesses for the atomic transfer is complete. The atomic transfer iscomplete when the Intel ® 80200 processor generates a write transaction. Note, between the initiallocked read transaction and write transaction, the Intel ® 80200 processor may generate one or moreread transactions (behavior of Intel ® 80200 processor). The CIU keeps asserting the signal tosignify atomicity, until the CIU completes the atomic transfer by generating the write transaction.When this signal is asserted, the Internal Bus Arbiter guarantees atomicity of accesses bypreventing other agents from using the internal bus.See Chapter 7, Intel ® 80312 I/O Companion Chip Arbitration for additional information.Atomic accesses to the ATUs are not supported.Developer’s Manual 8-5