Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.3 Primary ATU Command Register - PATUCMDATU Command Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2 and in most cases, affect the behavior of the primary PCI ATU and devices on theprimary PCI bus.Table 5-30.Primary ATU Command Register - PATUCMDIOPAttributes15 12 8 4 0rv rv rv rv rv rv rw rw ro rw ro rw ro rw rw roPCIAttributesrvrvrvrvrvrvrwrwrorwrorwrorw rwroIntel ® 80200 Processor Local Bus Address1204HPCI Configuration Address Offset04H - 05HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:10 000000 2 ReservedFast Back to Back Enable - When cleared, the ATU primary interface is not allowed to generate fast09 0 2 back-to-back cycles on its bus.P_SERR# Enable - When cleared, the ATU primary interface is not allowed to assert P_SERR# on the08 0 2 primary PCI interface.07 0 2 Wait Cycle Control - controls address/data stepping. Not implemented and a reserved bit field.Parity Error Response - When set, the primary ATU and DMA channels 0 and 1 take normal action when06 0 2 a parity error is detected. When cleared, parity checking is disabled.VGA Palette Snoop Enable - The primary ATU interface does not support I/O writes and therefore, does05 0 2 not perform VGA palette snooping.Memory Write and Invalidate Enable - When set, DMA channels 0 and 1 may generate MWI commands.04 0 2 When clear, DMA channels 0 and 1 use Memory Write commands instead of MWI.Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. Not03 0 2 implemented and a reserved bit field.02 0 2Bus Master Enable - The primary ATU interface can act as a master on the PCI bus. When cleared,disables the device from generating PCI accesses. When set, allows the device to behave as a PCI busmaster.This enable bit also controls DMA channels 0 and 1 master interface. The bit must be set beforeinitiating a DMA transfer on the PCI bus.Memory Enable - Controls the primary ATU interface’s response to PCI memory addresses. When01 0 2 cleared, the ATU interface does not respond to any memory access on the PCI bus.I/O Space Enable - Controls the ATU interface response to I/O transactions on the primary side. Not00 0 2 implemented and a reserved bit field.Developer’s Manual 5-63