Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11.1.2 Address Parity Errors on Secondary InterfaceWhen an address parity error occurs on the Secondary interface of the bridge unit, the Intel ® 80312I/O companion chip performs the following actions based on the constraints specified:• When the Secondary Parity Error Response Enable bit in the Bridge Control Register (BCR) isset, the Secondary bridge interface will not claim the transaction by not assertingS_DEVSEL#, allowing a master abort to occur.When the Secondary Parity Error Response Enable bit in the BCR is cleared, theSecondary bridge interface takes normal action and allows the transaction to proceed.• Assert P_SERR# on the Primary interface when the SERR# Enable bit in the PCR is set andSecondary Parity Error Response Enable bit and the Secondary SERR# enable bit in the BCRare set.• Set the Signaled System Error bit in the PSR when the SERR# Enable bit in the PCR is set andSecondary Parity Error Response Enable bit in the BCR is set. When the Signaled SystemError bit in the PSR is set and the P_SERR# Asserted Interrupt Mask is clear in the SDER, setthe P_SERR# Asserted bit in the PBISR• Set the Detected Parity Error bit in the SSR. When the Detected Parity Error bit in the SSR isset and the Secondary Detected Parity Error Interrupt Mask bit in the SDER is clear, setDetected Parity Error bit in the SBISR.While forwarding a DAC cycle upstream, the bridge may detect an address parity error in any ofthe four different parts of the DAC address phase in which parity information is encoded. When anaddress parity error is detected in these cases, the bridge will forward the DAC using bad addressparity for all possible parts of the forwarded transaction. This eliminates the possibility of anaddress parity being filtered out by the bridge in the event it is converted from a 64-bit transactionto a 32-bit transaction.Developer’s Manual 4-67