Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.8.2 Delayed Write TransactionA delayed write transaction is initiated by an agent on the initiating PCI bus and is targeted at a PCIagent on the target PCI buses. I/O and Configuration writes as well as memory writes with postingdisabled are processed as delayed writes. The delayed write request address is propagated from theinitiating PCI bus to the target PCI bus through a Transaction Queue. The delayed write requestdata is propagated to the target bus in a Delayed Write Completion (DWC) Queue. Completionstatus is returned to the master on the initiating bus during a retry cycle.The data flow for a delayed write transaction on the PCI bus is summarized in the followingstatements:• The Bridge claims the PCI write transaction when the PCI address is within an addresswindow defined by a Base/Limit register pair, the Delayed Write Completion Queue isavailable (when DWC is free, the associated Transaction Queue is free by architecturaldefinition), and it is a delayed write PCI transaction (I/O writes, Configuration Writes,Memory Writes with posting disabled).• The address is written to the Transaction Queue in anticipation of capturing the data for thedelayed write request.• When an address parity error is detected (when enabled), the Transaction Queue is cleared andthe transaction is allowed to master-abort. SERR# is asserted when enabled and on thePrimary bus.• The assertion of STOP#, to Retry the transactions, by the bridge unit is delayed until theassertion of PAR by the master so parity can be calculated. when parity is good, thetransaction is retried and the delayed write request can proceed to the target interface.• When a data parity error is detected and parity response is enabled, the transaction is claimed(not retried) with the assertion of TRDY# and PERR# is asserted when enabled. The delayedwrite request is cleared from the queues and is not forwarded to the target interface.• When subsequent transactions from the master on the initiating bus are inside the addresswindow, the DWC is not cleared, and there is no cycle match or the write has not completed onthe target interface (!Write_Complete), the transaction is retried immediately.• When subsequent transactions are inside the address window, the DWC is not cleared, there isa cycle match, and the transaction has already completed on the target bus, then the bridge unitslave interface will compare the write data from the master with the write data that was used inthe delayed request cycle. When the data matches (with no parity error detected) then thestatus seen on the target bus is returned and a disconnect is performed. Note that the statusreturned is exactly what was seen from the target on the target bus i.e. target-abort, parity erroror normal completion.• When a parity error is detected from the data being written from the initiating master, thebridge slave interface will claim the transaction and assert PERR# when enabled. Since thedata has not matched with the data from the write request cycle, the transaction remainsenqueued.Developer’s Manual 4-57