Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.8 ATU Latency Timer Register - ATULTATU Latency Timer Register bit definitions apply to both the primary and secondary PCIinterfaces.Table 5-35.ATU Latency Timer Register - ATULTIOPAttributes7 4 0rw rw rw rw rw ro ro roPCIAttributesrw rw rw rw rwrororoIntel ® 80200 Processor Local Bus Address120DHPCI Configuration Address Offset0DHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionProgrammable Latency Timer - This field varies the latency timer for the primary interface from 0 to 24807:03 00000 2 clocks.Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for02:00 000 2 the latency timer.Developer’s Manual 5-69