Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.6.6.2 Target Abort on the Internal BusTarget Aborts can be seen by the internal bus master interface during inbound read and write operationsto the memory controller. They are signaled as a slave device in response to a target abort encounteredduring outbound read. During inbound operations, the memory controller is capable of signalling atarget abort when a multi-bit, unrecoverable ECC error is encountered. This can occur during writes ofless than 64-bits and during any read operation. During outbound read operations, a delayed read cycle,that is target aborted on the PCI bus, results in a target abort being driven back to the CIU on the internalbus. Outbound writes do not see target aborts because they are always fully posted.The following action with the given constraints are performed by the primary and secondary ATUswhen a target abort is detected by the internal master interface during an inbound write transaction:Table 5-20.Target Abort During an Inbound Write TransactionPrimary ATUIf the Primary Inbound Error P_SERR# Enable bit isset and the P_SERR# Enable bit is set in thePATUCMD, assert P_SERR# on the primaryinterface. If both bits aren’t set, take no action.If P_SERR# is asserted, set the P_SERR# Assertedbit in the PATUSR.If P_SERR# is asserted and the PATU P_SERR#Asserted Interrupt Mask bit in the PATUIMR is clear,set the P_SERR# Asserted bit in the PATUISR. If set,no action.If P_SERR# is asserted and the PATU P_SERR#Detected Interrupt Mask bit in the ATUCR is clear, setthe P_SERR# Detected bit in the PATUISR. If set, noactionIf the inbound write transaction is still active on theprimary PCI interface, notify the primary PCI slaveinterface to disconnect the transaction.Secondary ATUIf the Secondary Inbound Error S_SERR# Enable bitis set, and the S_SERR# Enable bit is set in theSATUCMD, assert S_SERR# on the secondaryinterface. If both bits aren’t set, take no action.If S_SERR# is asserted, set the S_SERR# Assertedbit in the SATUSR.If S_SERR# is asserted and the SATU S_SERR#Asserted Interrupt Mask bit in the SATUIMR is clear,set the S_SERR# Asserted bit in the SATUISR. If set,no action.If S_SERR# is asserted and the SATU S_SERR#Detected Interrupt Mask bit in the ATUCR is clear, setthe S_SERR# Detected bit in the SATUISR. If set, noactionIf the inbound write transaction is still active on theprimary PCI interface, notify the secondary PCI slaveinterface to disconnect the transaction.The Memory Controller is responsible for creating the Intel ® 80200 processor IRQ# interrupt. Theinbound write queue (IWQ) is not cleared and the ATU internal bus master interface re-arbitratesfor the internal bus and eventually drain the transaction which was target aborted from the queue.The following action with the given constraints are performed by the primary and secondary ATUswhen a target abort is detected by the internal master interface during an inbound read transaction:Table 5-21.Target Abort During an Inbound Read TransactionPrimary ATUIf the data word which was target aborted on theinternal bus is actually requested and delivered on theprimary PCI Bus, and the Primary ATU ECC TargetAbort Enable bit is set in the PATUIMR, a target abortis returned to the PCI initiator on that data word. If thePrimary ATU ECC Target Abort Enable bit is clear inthe PATUIMR, a disconnect with data is returned tothe PCI initiator during the data word that was targetaborted on the internal bus.Secondary ATUIf the data word which was target aborted on theinternal bus is actually requested and delivered on thesecondary PCI Bus, and the Secondary ATU ECCTarget Abort Enable bit is set in the SATUIMR, atarget abort is returned to the PCI initiator on that dataword. If the Secondary ATU ECC Target Abort Enablebit is clear in the SATUIMR, a disconnect with data isreturned to the PCI initiator during the data word thatwas target aborted on the internal bus.The Memory Controller is responsible for creating the IRQ# interrupt to the Intel ® 80200processor. Note target aborts are signalled on a Qword basis. If either Dword of a Qword targetaborts, both are considered to have target aborted.5-50 Developer’s Manual