Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.4 Inbound Interrupt Status Register - IISRThe Inbound Interrupt Status Register (IISR) contains hardware interrupt status. It records thestatus of Intel ® 80200 processor interrupts generated by the Message Registers, DoorbellRegisters, and the Circular Queues. All interrupts are routed to the FIQ# interrupt input of theIntel ® 80200 processor, except for the IRQ Doorbell Interrupt and the Outbound Free Queue Fullinterrupt; these two are routed to the IRQ interrupt input. The generation of interrupts recorded inthe Inbound Interrupt Status Register may be masked by setting the corresponding bit in theInbound Interrupt Mask Register. Some bits in this register are Read Only. For those bits, theinterrupt must be cleared through another register.Table 6-10.Inbound Interrupt Status Register - IISR3128 24 20 16 12 8 4 0PCI IOPAttributes AttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrorororororcrcrcrcIISRIntel ® 80200 Processor Local Bus Address1324HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:07 0000000H 0 2 Reserved06 0 2Index Register Interrupt - This bit is set by the MU hardware when an Index Registeris written after a PCI transaction.05 0 2Outbound Free Queue Full Interrupt - This bit is set when the Outbound Free HeadPointer becomes equal to the Tail Pointer and the queue is full. An IRQ interrupt isgenerated for this condition.Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound04 0 2 Post Queue has been written.03 0 2 Register is set. To clear this bit (and the interrupt), the IRQ Interrupt bit of the InboundIRQ Doorbell Interrupt - This bit is set when the IRQ Interrupt of the Inbound DoorbellDoorbell Register must be clear.02 0 2Inbound Doorbell Interrupt - This bit is set when at least one FIQ2 Interrupt bit in theInbound Doorbell Register is set. To clear this bit (and the interrupt), the FIQ2 Interruptbits in the Inbound Doorbell Register must all be clear.Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound01 0 2 Message 1 Register has been written.Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound00 0 2 Message 0 Register has been written.Developer’s Manual 6-21