Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPerformance Monitoring UnitTable 11-7. Event Monitoring Interrupt Status Register (EMISR) (Sheet 2 of 2)IOPAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrcrcrcrcrcrcrcrcrcrcPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na31 28 24 20 16 12 8 4 0Intel ® 80200 Processor Local Bus AddressAttribute Legend: RW = Read/Write0000 1108HRV = Reserved RC = Read ClearPR = Preserved RO = Read OnlyRS = Read/Set NA = Not AccessibleBit Default Description7 0 2Bit value indicates the status of the Programmable Event Counter 7 (PEC7) during event monitoring.When clear (0), no PEC7 overflow interrupt is pending. When set (1), a PEC7 overflow interrupt ispending.6 0 2Bit value indicates the status of the Programmable Event Counter 6 (PEC6) during event monitoring.When clear (0), no PEC6 overflow interrupt is pending. When set (1), a PEC6 overflow interrupt ispending.5 0 2Bit value indicates the status of the Programmable Event Counter5 (PEC5) during event monitoring.When clear (0), no PEC5 overflow interrupt is pending. When set (1), a PEC5 overflow interrupt ispending.4 0 2Bit value indicates the status of the Programmable Event Counter4 (PEC4) during event monitoring.When clear (0), no PEC4 overflow interrupt is pending. When set (1), a PEC4 overflow interrupt ispending.Bit value indicates Programmable Event Counter3 (PEC3) status during event monitoring. When clear3 0 2 (0), no PEC3 overflow interrupt is pending. When set (1), a PEC3 overflow interrupt is pending.2 0 2 When clear (0), no PEC2 overflow interrupt is pending. When set (1), a PEC2 overflow interrupt isBit value indicates the status of the Programmable Event Counter2 (PEC2) during event monitoring.pending.1 0 2Bit value indicates the status of the Programmable Event Counter1 (PEC1) during event monitoring.When clear (0), no PEC1 overflow interrupt is pending. When set (1), a PEC1 overflow interrupt ispending.Bit value indicates the status of the Global Time Stamp Counter (GTS) during event monitoring. When0 0 2 clear (0), no GTS overflow interrupt is pending. When set (1), a GTS overflow interrupt is pending.11-26 Developer’s Manual
Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.6.4 Global Time Stamp Register (GTSR)The Global Time Stamp register (GTSR) is a 32-bit, read-only register. Writes to the GTSR have noeffect. The GTSR contains the current count value of the Global Time Stamp Counter. The counterfrequency is one-quarter the Internal Bus clock frequency. When a new mode is chosen by writinga value to the ESR, this register is reset to zero. This register can be read at any time and returns thecurrent count value.Table 11-8.Global Time Stamp Register - GTSRIOPAttributesrorororororororororororororororororororororororororororororororoPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na31 28 24 20 16 12 8 4 0Intel ® 80200 Processor Local Bus AddressAttribute Legend: RW = Read/Write0000 1110HRV = Reserved RC = Read ClearPR = Preserved RO = Read OnlyRS = Read/Set NA = Not AccessibleBit Default Description31:00 XThis is a 32-bit, read-only register. When accessed, it returns the current count value in the Global TimeStamp Counter.Developer’s Manual 11-27
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Application Accelerator Unit 10This
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Intel 80312 I/O Companion Chip - ECEE

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