Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.17 Memory Base Register - MBRMemory Base Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2. The Memory Base Register defines the bottom address (inclusive) of amemory-mapped I/O address range (non-prefetchable) that is used to determine when to forwardmemory transactions from one side of the bridge to the other. The Memory Base Register must beprogrammed before the Memory Space Enable bit of the Primary Command Register (PCR) is set.The upper 12 bits correspond to AD[31:20] of 32-bit addresses. For the purposes of addressdecoding, the bridge assumes that AD[19:0], the lower 20 address bits of the memory base address,are zero. This means that the bottom of the defined address range will be aligned on a 1 Mbyteboundary.The VGA Enable bit in the BCR register forces the bridge to forward memory accesses in theaddress range from 0A0000H to 0BFFFFH from the Primary to Secondary and blocks addresses inthe same range from Secondary to Primary.Table 4-40.Memory Base Register - MBRIOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rw rw rw rwrvrvrvrvPCI Configuration Offset20 - 21HIntel ® 80200 Processor Local Bus Address0000 1020HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:04 000HMemory Base Address - This field is programmed with AD[31:20] of the bottom of the memory addressrange to be passed down the hierarchy by the bridge.03:00 0H Reserved.4-102 Developer’s Manual