Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.5.2 Inbound Post QueueThe Inbound Post Queue holds posted messages placed there by other processors for the Intel ®80200 processor to process. This queue is read from the queue tail by the Intel ® 80200 processor. Itis written to the queue head by external PCI agents. The tail pointer is maintained by the Intel ®80200 processor. The head pointer is maintained by the MU hardware.For a PCI write transaction that accesses the Inbound Queue Port, the MU writes the data to thelocal memory location address in the Inbound Post Head Pointer Register.When the data written to the Inbound Queue Port is written to local memory, the MU hardwareincrements the Inbound Post Head Pointer Register.An Intel ® 80200 processor interrupt may be generated when the Inbound Post Queue is written.The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates theinterrupt status. The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. Theinterrupt can be masked by the Inbound Interrupt Mask Register. When the Inbound Post Queuereaches a full state (head pointer equals tail pointer), the PCI interface retries all further writes untilsoftware increments the tail pointer or the Inbound Post Queue Interrupt bit is cleared. To preventan indefinite retry, software must be aware of the state of the Inbound Post Queue Interrupt Maskbit to guarantee that the full condition is recognized by the Intel ® 80200 processor. In addition, toguarantee that the queue is not overwritten, software must remove data from the tail of the queuebefore clearing the interrupt (and incrementing the tail pointer).From the time that the PCI write transaction is received until the data is written in local memoryand the Inbound Post Head Pointer Register is incremented, any PCI transaction that attempts toaccess the Inbound Post Queue Port is signalled a Retry.The Intel ® 80200 processor may read messages from the Inbound Post Queue by reading the datafrom the local memory location pointed to by the Inbound Post Tail Pointer Register. The Intel ®80200 processor must then increment the Inbound Post Tail Pointer Register. When the InboundPost Queue is full, the hardware retries any PCI writes until a slot in the queue becomes available,by the Intel ® 80200 processor either clearing the inbound post queue interrupt or incrementing thetail pointer. When the head pointer and tail pointer become equal, software must clear the inboundpost queue interrupt bit to avoid indefinite retries by the MU.6-12 Developer’s Manual