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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Memory Controller3.2.3.9 SDRAM Refresh CycleSince the SDRAM is a dynamic memory, the MCU issues a refresh cycle periodically. The intervalof these refresh cycles is programmable in the RFR register. The SDRAM device generates therefresh address internally. The MCU initiates two sequential refresh cycles (one per bank) after theMCUs refresh timer expires and any current transaction is complete. The waveform in Figure 3-15illustrates the case where the refresh timer expires in the middle of an incomplete read cycle.Figure 3-15.Refresh Following a Read CycleDCLK0 1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 17 18 19SCE[0]#SCE[1]#SRAS#SCAS#SWE#SA[12:0]COLDQ[71:0] D 2 D 3 D 4 D 5 D 6 D 7D 8D 9SDQM[7:0] 00 FFRead inprogressRefreshcounter expiresT dqzPrechargeT rpRefresh Bank 0TRefresh Bank 1 rcReady for next transactionon internal bus• Once the refresh timer expires, the MCU knows that a refresh cycle is necessary.— The refresh timer continues to count for the next refresh cycle.• MCU allows the current read transaction to complete.— Since the MCU is currently reading from the SDRAM array, the refresh cycle is queueduntil the transaction is complete.• MCU closes all open pages with a precharge-all command to all populated SDRAM banks.— The MCU resets the page register valid bits.• The MCU issues an auto-refresh command to SDRAM bank 0.— This command affects all internal leaves.• In the next cycle, the MCU issues an auto-refresh command to SDRAM bank 1.• After T rc cycles, the MCU can service a new transaction or another refresh cycle.The refresh timer value is programmed with the RFR depending on the internal bus frequency. TheRFR should be programmed to 600H. The longest possible internal bus transaction is writing a2Kbyte page where each data cycle results in a read-modify-write due to partial writes (seeSection 3.2.4.2, “ECC Generation for Partial Writes” on page 3-28). Such a transaction couldpotentially require queueing two refresh cycles.3-26 Developer’s Manual

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