Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMessaging UnitFigure 6-3 provides a more detailed diagram of the usage of the Circular Queues.Figure 6-3.Circular Queue OperationHigh Address MemoryExternalPCIAgentWriteReadOutboundQueue PortOutboundFreeIncremented byHardwareHead PointerTail PointerIntel ®80200ProcessorReadWriteOutboundPostIncremented by80200 ProcessorIncremented by80200 ProcessorHead PointerTail PointerHigh Address MemoryIncremented by HardwareExternalPCIAgentWriteReadInboundQueue PortInboundPostIncremented byhardwareHead PointerTail Pointer80200ProcessorReadWriteInboundFreeIncremented by80200 ProcessorIncremented by80200 ProcessorHead PointerTail PointerLow Address MemoryIncremented by HardwareIntel ® 80200 Processor Local MemoryA8294-016-10 Developer’s Manual
Intel ® 80312 I/O Companion ChipMessaging Unit6.5.1 Inbound Free QueueThe Inbound Free Queue holds free inbound messages placed there by the Intel ® 80200 processorfor other processors to use. This queue is read from the queue tail by external PCI agents. It iswritten to the queue head by the Intel ® 80200 processor. The tail pointer is maintained by the MUhardware. The head pointer is maintained by the Intel ® 80200 processor.For a PCI read transaction that accesses the Inbound Queue Port, the MU attempts to read the data atthe local memory address in the Inbound Free Tail Pointer:• When the queue is not empty (head and tail pointers are not equal), or full (head and tailpointers are equal but the head pointer was last written by software), the data is returned.• When the queue is empty (head and tail pointers are equal), the value of -1 (FFFF.FFFFH) isreturned.• When the queue was not empty and the MU succeeded in returning the data at the tail, the MUhardware must increment the value in the Inbound Free Tail Pointer Register.To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipateaccesses to the Inbound Free Queue. The MU hardware prefetches the data at the tail of theInbound Free Queue and loads it into an internal prefetch register. When the PCI read accessoccurs, the data is read directly from the prefetch register.The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the headand tail pointers are equal and the queue is empty. To update the prefetch register when messagesare added to the queue and it becomes non-empty, the prefetch mechanism automatically starts aprefetch when the prefetch register contains FFFF.FFFFH and the Inbound Free Head PointerRegister is written. The Intel ® 80200 processor needs to update the Inbound Free Head PointerRegister when it adds messages to the queue.A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch isstarted, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retryuntil the prefetch is completed.The Intel ® 80200 processor may place messages in the Inbound Free Queue by writing the data tothe local memory location pointed to by the Inbound Free Head Pointer Register. The processormust then increment the Inbound Free Head Pointer Register.Developer’s Manual 6-11
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