Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipGeneral Purpose Input Output (GPIO)13.2.2 GPIO Input Data Register - GPIDThe GPIO Input Data Register reflects the state of the appropriate IRQ bus pin following thedeassertion of P_RST#.Table 13-2.GPIO Input Data Register - GPIDIOPAttributes7 4 0ro ro ro ro ro ro ro roPCIAttributesnanananananananaIntel ® 80200 Processor Local Bus Address0000 1720HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07 0 2 GPIO7 Input Data -- This bit reflects the state of the GPIO[7] pin following the deassertion of P_RST#.06 0 2 GPIO6 Input Data -- This bit reflects the state of the GPIO[6] pin following the deassertion of P_RST#.05 0 2 GPIO5 Input Data -- This bit reflects the state of the GPIO[5] pin following the deassertion of P_RST#.04 0 2 GPIO4 Input Data -- This bit reflects the state of the GPIO[4] pin following the deassertion of P_RST#.03 0 2 GPIO3 Input Data -- This bit reflects the state of the GPIO[3] pin following the deassertion of P_RST#.02 0 2 GPIO2 Input Data -- This bit reflects the state of the GPIO[2] pin following the deassertion of P_RST#.01 0 2 GPIO1 Input Data -- This bit reflects the state of the GPIO[1] pin following the deassertion of P_RST#.00 0 2 GPIO0 Input Data -- This bit reflects the state of the GPIO[0] pin following the deassertion of P_RST#.13-4 Developer’s Manual