Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.32 Secondary Memory Base Register - SMBRSecondary Memory Base Register bits are used to define a private address space on the SecondaryPCI bus when the Private Address Space Enable bit in the SDER is set. The Secondary MemoryBase Register defines the bottom address (inclusive) of a memory-mapped address range that isused to determine when to not forward transactions from the Secondary to Primary interface. TheSecondary Memory Base Register must be programmed with a valid value before the PrivateAddress Space Enable bit in the SDER is set. The upper 12 bits correspond to S_AD[31:20] of32-bit addresses. For the purposes of address decoding, the bridge assumes that S_AD[19:0],thelower 20 address bits of the memory base address, are zero. This means that the bottom of thedefined address range will be aligned on a 1 Mbyte boundary.Table 4-53.Secondary Memory Base Register - SMBRIOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rwrw rw rwrvrvrvrvPCI Configuration Offset58 - 59HIntel ® 80200 Processor Local Bus Address0000 1058HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:04 000HSecondary Memory Base Address - This field is programmed with S_AD[31:20] of the bottom of theSecondary memory address range that is not passed from the Secondary to Primary interface whenprivate address space is enabled.03:00 0H Reserved.Developer’s Manual 4-119