Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.4 Doorbell RegistersThere are two Doorbell Registers: the Inbound Doorbell Register and the Outbound DoorbellRegister. The Inbound Doorbell Register allows external PCI agents to generate interrupts to theIntel ® 80200 processor. The Outbound Doorbell Register allows the Intel ® 80200 processor togenerate a PCI interrupt. Both Doorbell Registers may generate interrupts whenever a bit in theregister is set.6.4.1 Outbound DoorbellsWhen the Outbound Doorbell Register is written by the Intel ® 80200 processor, an interrupt maybe generated on P_INTA#, P_INTB#, P_INTC#, or P_INTD# interrupt pins. An interrupt isgenerated when any bits in the doorbell register is written to a value of “1”. Writing a value of “0”to any bit does not change the value of that bit and does not cause an interrupt to be generated.Once a bit is set in the Outbound Doorbell Register, it cannot be cleared by Intel ® 80200 processor.Which PCI interrupt pin used is determined by the value of the ATU Interrupt Pin Register(Chapter 5, “PCI Address Translation Unit”).The interrupt is recorded in the Outbound Interrupt Status Register.The interrupt may be masked by the Mask bits in the Outbound Interrupt Mask Register. When theMask bit is set for a particular bit, no interrupt is generated for that bit. The Outbound InterruptMask Register affects only the generation of the interrupt and not the values written to theOutbound Doorbell Register.The interrupt is cleared when an external PCI agent writes a value of “1” to the bits in theOutbound Doorbell Register that are set. Writing a value of “0” to any bit does not change thevalue of that bit and does not clear the interrupt.In summary, the Intel ® 80200 processor generates an interrupt by setting bits in the OutboundDoorbell Register and external PCI agents clear the interrupt by also setting bits in the same register.6.4.2 Inbound DoorbellsWhen the Inbound Doorbell Register is written by an external PCI agent, an interrupt may begenerated to the Intel ® 80200 processor. An interrupt is generated when any of the bits in thedoorbell register is written to a value of “1”. Writing a value of “0” to any bit does not change thevalue of that bit and does not cause an interrupt to be generated. Once a bit is set in the InboundDoorbell Register, it cannot be cleared by any external PCI agent.The interrupt is recorded in the Inbound Interrupt Status Register.The interrupt may be masked by the Inbound Doorbell Interrupt Mask bit in the Inbound InterruptMask Register. When the mask bit is set for a particular bit, no interrupt is generated for that bit.The Inbound Interrupt Mask Register affects only the generation of the interrupt and not the valueswritten to the Inbound Doorbell Register.One bit in the Inbound Doorbell Register is reserved for an IRQ# interrupt.The interrupt is cleared when the Intel ® 80200 processor writes a value of “1” to the bits in theInbound Doorbell Register that are set. Writing a value of “0” to any bit does not change the valueof that bit and does not clear the interrupt.6-6 Developer’s Manual