Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.3.3 Memory Controller Response to I_RST#The memory controller assumes a power failure condition whenever I_RST# is asserted. Note thatI_RST# is asserted in response to the assertion of P_RST#.WhenP_RST# indicates a true powerfailure, then battery-backup power is supplied to the SDRAM array. When P_RST# indicates anycondition other than a power failure, the SDRAM array is powered down and any attempt to issuethe self-refresh commandisignoredbythememory.Due to the high loading on SCKE and the requirement of 100 MHz operation, the memorycontroller must drive two copies to the SDRAM DIMM. The board layout distributes the twoSCKE[1:0] signals between the two SDRAM banks equally.Refer to Figure 3-21 for a high-level state machine representation illustrating the memorycontroller’s behavior during a power failure condition.Figure 3-21.Power Failure State MachineP_RST#transitions to 0Issueself-refreshcommand toSDRAMIgnore theInternal Busand wait for8 cyclesIssueauto-refreshcommand toSDRAMIssueprecharge-allcommand toSDRAMA6813-01Once the memory controller detects the assertion of I_RST#, the memory controller:• Ignore the internal bus. The internal bus is invalid during I_RST# so the memory controllershould not assume any valid state.• Wait for eight clocks to allow any previous SDRAM bus activity (i.e., read burst) to completebefore the memory controller issues the precharge-all command.• Deactivate all SDRAM leaves with the precharge-all command.• Issue an auto-refresh command and wait T rc (8) clocks.• Issue a self-refresh command to the SDRAM devices and continue to deassert SCKE[1:0].Developer’s Manual 3-37