Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.5.2 64-Bit Operation with 32-Bit TargetsWhen a 64-bit transfer is requested by the PCI master interfaces by the assertion of REQ64#, itisnot guaranteed that the target of the transaction is capable of performing the 64-bit request. In thiscase, ACK64# remains deasserted when the target asserts DEVSEL# to claim the transaction.When a target signals that is cannot complete the transaction using 64-bit transfers, the ATU masterinterfaces are responsible for completing the transactions as a 32-bit master. Two possibleconditions arise from a 32-bit target which does not respond with ACK64#:1. ACK64# deasserted but a burst can be sustained2. ACK64# deasserted but a burst can not be sustainedIf a 32-bit target does not respond with ACK64# and STOP#, it is capable of continuing a burst asa 32-bit target. For memory read requests, the ATU interfaces changes to 32-bit operation by onlyexpectingreaddataonthelowerbytelanes,AD[31:0]. The master interfaces continue requestingread data (by the continued asserting of IRDY#) as 32-bit masters. No master completions areprematurely signaled due to 32-bit target response. For memory write operations, the masterinterface may already have the first data phase on the bus by the time it is detected that ACK64#has not been asserted. The PATU and SATU master interfaces discontinue driving data on the upper4 bytes during the second data phase. The second data phase of the burst now contains the datafrom the high 4 bytes of the first data phase. The master interface stops driving the AD[63:32] andC/BE[7:4]# during data phase 2 and all subsequent data phases of the burst write transfer. SeeFigure 5-9 for a diagram of this transaction. As a note, a disconnect after the first data phase of theburst transfer write results in the continuation of the write transaction as a 32-bit master only (noREQ64#). This works similar to the write transfer disconnected in the first data phase described inthe next paragraph.If a 32-bit target does not respond with ACK64# but asserts STOP#, the target does not continuethe burst. If a read or write request is made and STOP# without TRDY# is signaled (Retry), themaster interface must repeat the original read or write request as a 64-bit transaction. If the targetsignals a disconnect with data (STOP# and TRDY#) on a write transaction, then only the lower 4bytes of the 8 byte transfer have been delivered. The master state machines of the ATUs repeat therequest as a 32-bit master (no REQ64# assertion) using the upper 4 bytes of data from thedisconnected transaction on AD[31:00] and the next address (i.e. when address 00H was used inthe first 64-bit request, address 04H is used in the next 32-bit request). A disconnect from a 32-bittarget before an odd address results in a new transaction (when required) as a 32-bit master. Adisconnect from a 32-bit target before an even address results in a new transaction as a 64-bitmaster (when required).Note that 32-bit targets create special circumstances for FRAME# signaling. For 64-bit, singleQword transfers, FRAME# is driven low and then high immediately in the next clock signalinglast data phase. Due to the potential of requiring two 32-bit data phases to complete what wasoriginally intended as one 64-bit data phase, this is not possible. FRAME# must not be deasserteduntil after ACK64# is returned or not.Developer’s Manual 5-27