Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipTest FeaturesTable 14-3.IEEE InstructionsInstruction /RequisiteOpcodeDescriptionextestIEEE 1149.1Requiredsample/preloadIEEE 1149.1RequiredidcodeIEEE 1149.1OptionalbypassIEEE 1149.1Requiredextest initiates testing of external circuitry, typically board-level interconnects andoff chip circuitry. extest connects the boundary-scan register between TDI and TDOin the Shift_DR state only. When extest is selected, all output signal pin values aredriven by values shifted into the boundary-scan register and may change only on0000 2 the falling edge of TCK in the Update_DR state. Also, when extest is selected, allsystem input pin states must be loaded into the boundary-scan register on therising-edge of TCK in the Capture_DR state. Values shifted into input latches in theboundary-scan register are never used by the processor internal logic.sample/preload performs two functions:• When the TAP controller is in the Capture-DR state, the sample instructionoccurs on the rising edge of TCK and provides a snapshot of the componentnormal operation without interfering with that normal operation. The instructioncauses boundary-scan register cells associated with outputs to sample the0001 2 value being driven by or to the processor.• When the TAP controller is in the Update-DR state, the preload instructionoccurs on the falling edge of TCK. This instruction causes the transfer of dataheld in the boundary-scan cells to the slave register cells. Typically the slavelatched data is applied to the system outputs via the extest instruction.idcode is used in conjunction with the device identification register. It connects thedevice identification register between TDI and TDO in the Shift_DR state. When0010 2 selected, idcode parallel-loads the hard-wired identification code (32 bits) into thedevice identification register on the rising edge of TCK in the Capture_DR state.NOTE: Device identification register is not altered by data being shifted in on TDI.bypass instruction selects the one-bit bypass register between TDI and TDO pinswhile in SHIFT_DR state, effectively bypassing the processor test logic. 0 2 iscaptured in the CAPTURE_DR state. This is the only instruction that accesses the1111 2 bypass register. While this instruction is in effect, all other test data registers haveno effect on system operation. Test data registers with both test and systemfunctionality perform their system functions when this instruction is selected.highz 1000 2Executing highz generates a signal that is read on the rising-edge of RESET#.When this signal is found asserted, the device is put into the ONCE mode (all outputpins are floated). Also, when this instruction is active, the Bypass register isconnected between TDI and TDO. This register can be accessed via the JTAGTest-Access Port throughout the device operation. Access to the Bypass registercanalsobeobtainedwiththebypass instruction. highz provides an alternatemethod of entering ONCE mode.clamp 0100 2clamp instruction allows the state of the signals driven from the Intel ® 80312 I/Ocompanion chip pins to be determined from the boundary-scan register while theBYPASS register is selected as the serial path between TDI and TDO. Signalsdriven from the component pins does not change while the clamp instruction isselected.14-4 Developer’s Manual