Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitNote that both the Configuration Cycle Address and Data registers are non-burstable. Softwareshould only access these 4 registers with the single Dword read or write load/store operations. Aburst attempt to these registers may result in incorrect or unexpected behavior.Section 5.7, “Register Definitions” on page 5-55 describes an outbound configuration cycleaddress and data register definition and programming constraints. Note that while the programmingmodel uses the register interface for outbound configuration cycles, from a hardware standpoint,the address is entered into the OTQ, configuration write data goes through the OWQ andconfiguration read data is returned in the ORQ.Note:Outbound configuration cycle data registers are not physical registers. They are Intel ® 80312 I/Ocompanion chip memory mapped addresses used to initiate a transaction with the address in theassociated address register. Reads/writes to these registers return data from the PCI bus — not fromthe register.5.2.4 PCI Multi-Function Device Swapping/DisablingThe Intel ® 80312 I/O companion chip, in its default state, appears on the PCI bus as amulti-function device, with the Bridge as function 0 and the ATU as function 1. If necessary, thesefunction numbers can be swapped, or the Intel ® 80312 I/O companion chip can appear as a singlefunction device, with either the ATU or the Bridge designated as the single function. The swappingis accomplished by setting or clearing bit 21 of the ATU Configuration Register - ATUCR andsetting the value in the ATU Header Type Register - ATUHTR and the ATU Header Type Register- ATUHTR in the bridge from the Intel ® 80200 processor. The Intel ® 80312 I/O companion chipmust be in mode 3 (Intel ® 80200 processor executing and configuration cycles retried) whenexecuting the changes to these registers. The register settings are summarized in Table 5-3.Table 5-3.PCI Multi-Function Device Swapping/Disabling SummaryBridge HeaderType Register(HTR)ATU HeaderType Register(ATUHTR)ATUConfigurationRegister(ATUCR), Bit21Intel ® 80312I/O companionchip DeviceTypeBridgeFunctionNumberATU FunctionNumber1 1 0Multi-Function(Default)Function 0 Function 11 1 1 Multi-Function Function 1 Function 00 0 0 Single Function Function 0 Master-Aborts0 0 1 Single Function Master-Aborts Function 0Note:Configuring the Intel ® 80312 I/O companion chip as a single function device is only recommendedin situations where the host BIOS does not recognize multi-function devices and/or PCI-to-PCIBridge configuration headers. It is up to the user to handle/disable error reporting for the disabledunit.5-24 Developer’s Manual