Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.1.2 Inbound Write TransactionAn inbound write transaction is initiated by a PCI master (on either the primary or secondary PCIbus) and is targeted at either Intel ® 80312 I/O companion chip local memory or a Intel ® 80312 I/Ocompanion chip memory-mapped register.Data flow for an inbound write transaction on the PCI bus is summarized as:• The ATU claims the PCI write transaction when the PCI address is within the inboundtranslation window defined by the ATU Inbound Base Register and Inbound Limit Register.• When the IWQAD has at least one address entry available and the IWQ is not full and iscapable of accepting data (dependent upon the Memory Write Non-Full State Bits inSection 5.7.48, “Primary ATU Queue Control Register - PAQCR” on page 5-112 andSection 5.7.49, “Secondary ATU Queue Control Register - SAQCR” on page 5-113, theaddress is latched and the first data phase is accepted. When additional queue space isavailable, the slave interface continues accepting data until the IWQ reaches a full state. WhenREQ64# was driven by the initiator, data is accepted as 64-bit, otherwise a 32-bit transactionsis used.• When an address parity error is detected during the address phase of the transaction, theaddress parity error mechanisms are used. Refer to Section 5.6.1 for details of the addressparity error response. When a data parity error is detected while accepting data, the slaveinterface sets the appropriate bits based on PCI specification. No other action is taken. Refer toSection 5.6.2.4 for details of the inbound write data parity error response.• The PCI interface continues to accept write data until one of the following is true:— The initiator performs a master completion.— The IWQ becomes full. In this case, the PCI interface signals a Disconnect to the initiatorand returns to idle.• When a master abort or a memory controller multi-bit ECC error (target abort), occurs duringthe inbound transaction on the internal bus and the transaction is still active on the PCIinterface, the slave interface performs a disconnect, and SERR# is asserted based upon thesetting of the PATUIMR or SATUIMR, see Section 5.7.50, “Primary ATU Interrupt MaskRegister-PATUIMR”onpage5-114and Section 5.7.51, “Secondary ATU Interrupt MaskRegister-SATUIMR”onpage5-115.Once the PCI interface places a PCI address in the IWQAD and a 2 QWORD boundary is crossedor when the master disconnects on the PCI bus, the ATUs internal bus interface becomes aware ofthe inbound write. When there are additional write transactions ahead in the IWQ/IWQAD, thecurrent transaction remains posted until ordering and priority have been satisfied (Refer toSection 5.5.3) and the transaction is attempted on the internal bus by the ATU internal masterinterface. If there are no other write operations in the queue and ordering and the prioritymechanism supports it, the ATU attempts to immediately acquire the internal bus and allow writestreaming to occur. If the queue fills or the master completes before the first data phase is acceptedon the internal bus, streaming can not occur. The ATU does not insert target wait states nor do datamerging on the PCI interface to allow for streaming.Developer’s Manual 5-9