Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.5 Master Programming Examples12.5.1 Initialize Unit1. Write ICCR: Set clock count2. Write ISAR: Set slave address3. Write ICR: Enable all interrupts (except Arb Loss), set SCL Enable, set Unit Enable12.5.2 Write 1 Byte as a MasterNote:1. Write IDBR: Target slave address and R/W# bit (0 for write)2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:Read status register: IDBR Transmit Empty (set), Unit Busy (set), R/W# bit (clear)Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.The Arbitration Loss Detected bit may be set. Because the Arb Loss interrupt was disabled, whenarbitration was lost, an address retry would occur when the bus became free. Clear the ArbitrationLoss Detected bit when set.4. Send byte with STOPWrite IDBR: With data byte to sendWrite ICR: Clear START bit, Set STOP bit, Enable Arb Loss interrupt, Set Transfer Byte bit toinitiate the access5. Wait for Buffer empty interrupt. When interrupt arrives (Note: Unit is sending STOP):Read status register: IDBR Transmit Empty (set), Unit busy (set - maybe), R/W# bit (clear)Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.Clear ICR STOP bit (optional)Wait until Unit busy is clear before clearing the ICR SCL Enable bit. (optional)12.5.3 Read 1 Byte as a Master1. Write IDBR: Target slave address and R/W# bit (1 for read)2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer Byte bit toinitiate the access3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (set)Clear IDBR Transmit Empty bit to clear the interrupt.4. Read byte with STOPWrite ICR: Clear START bit, Set STOP bit, Enable arb loss interrupt, Set Ack/Nack bit(Nack), Set Transfer Byte bit to initiate the access5. Wait for Buffer full interrupt. When interrupt arrives (Note: Unit is sending STOP):Read status register: IDBR Receive Full (set), Unit Busy (set - maybe), R/W# bit (Set),Ack/Nack bit (Set)Clear IDBR Receive Full bit to clear the interrupt.Read IDBR data.Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional)Wait until Unit busy is clear before clearing the ICR SCL Enable bit. (optional)Developer’s Manual 12-23