Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.6.10 M5_DMA2_ownThis duration event counts the duration for which DMA Ch-2 is the master on the internal bus. Thecounter increments on every clock cycle during which Ch-2 is the bus master.11.3.6.11 M5_AA_gntThis occurrence event monitors the number of times the AA is granted the bus. It increments thecounter when the AA is the bus master. The counter is incremented once for every new transaction.For multi-cycle transactions, the counter increments once on the first cycle.11.3.6.12 M5_DMA0_gntThis occurrence event monitors the number of times DMA Ch-0 is granted the bus. It incrementsthe counter when DMA Ch-0 is the bus master. The counter is incremented once for every newtransaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.6.13 M5_DMA1_gntThis occurrence event monitors the number of times DMA Ch-1 is granted the bus. It incrementsthe counter when DMA Ch-1 is the bus master. The counter is incremented once for every newtransaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.6.14 M5_DMA2_gntThis occurrence event monitors the number of times DMA Ch-2 is granted the bus. It incrementsthe counter when DMA Ch-2 is the bus master. The counter is incremented once for every newtransaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.7 Mode 6: Intel ® 80312 I/O Companion Chip Bus and AgentsEventsProgramming Mode6 (M6) in the ESR enables performance monitoring on the Intel ® 80312 I/Ocompanion chip internal bus. In addition, performance monitoring is also done for selected agents.In this mode, the monitored agents are Primary Address Translation Unit (PATU), SecondaryAddress Translation Unit (SATU), and the Core Interface Unit (CIU). All counters are clocked atthe internal bus frequency. The following sections describe the monitored events in Mode 6.11.3.7.1 M6_core_acqThis duration event counts number of clocks spent by the CIU acquiring the internal bus interface. Thecounter increments every clock cycle after the CIU has requested use of the bus, but has not activelydriven the internal bus as a master. The counter also increments for all clock cycles when the agentRequest Signal is asserted, but bus ownership currently belongs to another master.11.3.7.2 M6_core_ownThis duration event counts the duration for which the CIU is the master on the internal bus. Thecounter increments on every clock cycle when the CIU is the bus master.Developer’s Manual 11-17