Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.1.5 Discard TimersThe ATUs implement discard timers for inbound delayed transactions. These timers preventdeadlocks when the initiator of a retried delayed transaction fails to complete the transaction within2 10 or 2 15 PCI clock cycles on the initiating bus. The timer starts counting when the delayedrequest becomes a delayed completion by completing on the internal bus. When the originatingmaster on the PCI bus has not retried the transaction before the timer expires, the completiontransaction is discarded.Discard timer values are controlled by the Bridge Control Register’s Primary Discard Timer Valuebit (for the primary ATU) and the Secondary Discard Timer Value bit (for the secondary ATU). ThePATU queues covered by discard timers are the P_IRQ and the P_IDWQ. The SATU queuecovered by discard timer is the S_IRQ. After discarding a transaction, the ATUs must set theDiscard Timer Status bit in the ATU Control Register. However, unlike the PCI to PCI Bridge Unit,the ATUs do not assert the P_SERR# signal after discarding a transaction.5.2.2 Outbound TransactionsOutbound transactions initiated by the Intel ® 80200 processor are either to the primary PCIinterface through the PATU or the secondary PCI interface through the SATU. As a PCI master, theATUs are capable of PCI I/O transactions, PCI memory reads (excluding the read hint commandsMRL and MRM), PCI memory writes (excluding MWI), configuration reads and writes, and DACcycles. Outbound transactions are performed as either 32-bit or a 64-bit PCI transactions. Refer toSection 5.2.5 for details on 64-bit operation. Outbound memory write operations are performed asposted operations and outbound memory read operations are all performed as delayed readoperations.Outbound transactions use a separate set of queues from inbound transactions. Outbound writeoperations have their address entered into the outbound transaction queue (OTQ) and their datainto the outbound write queue (OWQ). Outbound read transactions, performed as delayedoperations, use the same address queue, the OTQ, and get data returned into the outbound readqueue (ORQ). Refer to Section 5.5.2 for details of outbound queue architecture. Outboundconfiguration transactions use a special outbound port structure. Refer to Section 5.2.3 for details.For outbound transactions, the ATUs are slaves on the internal bus and masters on the PCI bus. PCImaster operation is defined in the PCI Local Bus Specification, Revision 2.2.5-14 Developer’s Manual