Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip4-55 Secondary Decode Enable Register - SDER ........................................................................4-1214-56 Queue Control Register- QCR...............................................................................................4-1234-57 Capability Identifier Register - Cap_ID ..................................................................................4-1244-58 Next Item Pointer Register - Next_Item_Ptr ..........................................................................4-1254-59 Power Management Capabilities Register - PMCR...............................................................4-1264-60 Power Management Control/Status Register - PMCSR ........................................................4-1274-61 PMCSR PCI-to-PCI Bridge Support - PMCSR_BSE .............................................................4-1285-1 ATU Command Support ............................................................................................................5-55-2 Outbound Read Fetch Sizes....................................................................................................5-215-3 PCI Multi-Function Device Swapping/Disabling Summary ......................................................5-245-4 Inbound Queues ......................................................................................................................5-325-5 Inbound Read Prefetch Data Sizes .........................................................................................5-345-6 Outbound Queues ...................................................................................................................5-355-7 ATU Inbound Data Flow Ordering Rules .................................................................................5-365-8 ATU Outbound Data Flow Ordering Rules ..............................................................................5-365-9 Address Parity Errors on the PCI Interface..............................................................................5-405-10 Outbound Read Data Parity Errors - Master............................................................................5-415-11 Outbound Write Data Parity Errors - Master............................................................................5-425-12 Inbound Write Data Parity Errors - Slave.................................................................................5-425-13 Master Aborts on the PCI Interface .........................................................................................5-445-14 Target Aborts on the PCI Interface ..........................................................................................5-455-15 Target Aborts on the Primary and Secondary ATUs ...............................................................5-455-16 SERR# Assertion on the Primary and Secondary ATUs .........................................................5-465-17 SERR# Detection On the Primary and Secondary ATUs ........................................................5-475-18 Master Abort During an Inbound Write Transaction ................................................................5-485-19 Master Abort During an Inbound Read Transaction ................................................................5-495-20 Target Abort During an Inbound Write Transaction .................................................................5-505-21 Target Abort During an Inbound Read Transaction.................................................................5-505-22 Primary ATU Error Reporting Summary - PCI Interface ..........................................................5-515-23 Secondary ATU Error Reporting Summary - PCI Interface .....................................................5-525-24 Primary ATU Error Reporting Summary - Internal Bus Interface.............................................5-535-25 Secondary ATU Error Reporting Summary - Internal Bus Interface ........................................5-545-26 Address Translation Unit Registers .........................................................................................5-575-27 ATU PCI Configuration Register Space...................................................................................5-595-28 ATU Vendor ID Register - ATUVID..........................................................................................5-615-29 Device ID Register - DID (Intel ® 80312 I/O Companion Chip) ................................................5-625-30 Primary ATU Command Register - PATUCMD .......................................................................5-635-31 Primary ATU Status Register - PATUSR.................................................................................5-645-32 ATU Revision ID Register - ATURID .......................................................................................5-665-33 ATU Class Code Register - ATUCCR .....................................................................................5-675-34 ATU Cacheline Size Register - ATUCLSR ..............................................................................5-685-35 ATU Latency Timer Register - ATULT.....................................................................................5-695-36 ATU Header Type Register - ATUHTR....................................................................................5-705-37 Primary Inbound ATU Base Address Register - PIABAR ........................................................5-715-38 ATU Subsystem Vendor ID Register - ASVIR .........................................................................5-725-39 ATU Subsystem ID Register - ASIR ........................................................................................5-735-40 Expansion ROM Base Address Register -ERBAR ..................................................................5-745-41 ATU Capabilities Pointer Register - ATU_Cap_Ptr..................................................................5-755-42 Memory Block Size Read Response Table .............................................................................5-765-43 ATU Base Registers and Associated Limit Registers..............................................................5-76Developer’s Manualxxiii