Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.7.10 M6_SBOFF_cntThis occurrence event counts the number of times the SATU asserts the SBOFF signal. Thisoccurrence event increments the counter on every instance of SBOFF assertion.11.3.7.11 M6_PATU_gntThis occurrence event monitors the number of times the PATU is granted the bus. This eventincrements the counter when the PATU is the bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.7.12 M6_SATU_gntThis occurrence event monitors the number of times the SATU is granted the bus. This eventincrements the counter when the SATU is the bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.7.13 M6_core_gntThis occurrence event monitors the number of times the Core Interface Unit (CIU) is granted thebus. This event increments the counter when the CIU is the bus master. The counter is incrementedonce for every new transaction. For multi-cycle transactions, the counter increments once on thefirst cycle.11.3.7.14 M6_ATU_retryThis occurrence event counts the number of retries issued by the Primary Address Translation Unit(PATU) on the primary PCI bus due to the inbound write queue being unable to accept a newtransaction. Retries issued by the PATU in response to configuration writes does not included inthis metric.11.3.8 Mode 7: Intel ® 80312 I/O Companion Chip Internal Bus,Secondary PCI Bus and Primary PCI Bus EventsProgramming Mode 7 (M7) in the ESR enables performance monitoring on the internal bus,secondary PCI bus and primary PCI bus. In addition, performance monitoring is done for externalagents (Intel ® 80312 I/O companion chip and external masters 0.5) on the secondary bus and forIntel ® 80312 I/O companion chip on the primary bus. Master0 designates the external secondaryPCI device that is connected to the REQ0 and GNT0 signals of the internal arbiter in the Intel ®80312 I/O companion chip. The nomenclature is similar for all other external PCI masters; Master1 through Master 5.In this mode, counters monitoring events on the internal bus are clocked at the internal busfrequency and counters monitoring PCI events are clocked at the respective PCI bus frequencies.The following sections describe the monitored events in Mode 7.Developer’s Manual 11-19